参数资料
型号: ATTINY43U-SU
厂商: Atmel
文件页数: 140/158页
文件大小: 0K
描述: MCU AVR 4K FLASH 8MHZ 20-SOIC
产品培训模块: ATtiny43U Overview
MCU Product Line Introduction
tinyAVR Introduction
标准包装: 37
系列: AVR® ATtiny
核心处理器: AVR
芯体尺寸: 8-位
速度: 8MHz
连通性: USI
外围设备: 欠压检测/复位,POR,PWM,温度传感器,WDT
输入/输出数: 16
程序存储器容量: 4KB(2K x 16)
程序存储器类型: 闪存
EEPROM 大小: 64 x 8
RAM 容量: 256 x 8
电压 - 电源 (Vcc/Vdd): 1.8 V ~ 5.5 V
数据转换器: A/D 4x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 20-SOIC(0.295",7.50mm 宽)
包装: 管件
产品目录页面: 613 (CN2011-ZH PDF)
配用: ATSTK600-TINYX3U-ND - STK600 SOCKET/ADAPTER TINYX3U
82
8048C–AVR–02/12
ATtiny43U
Figure 12-2. Counter Unit Block Diagram
Signal description (internal signals):
count
Increment or decrement TCNTn by 1.
direction
Select between increment and decrement.
clear
Clear TCNTn (set all bits to zero).
clk
Tn
Timer/Counter clock, referred to as clk
Tn in the following.
top
Signalize that TCNTn has reached maximum value.
bottom
Signalize that TCNTn has reached minimum value (zero).
Depending of the mode of operation used, the counter is cleared, incremented, or decremented
at each timer clock (clk
Tn). clkTn can be generated from an external or internal clock source,
selected by the Clock Select bits (CSn[2:0]). When no clock source is selected (CSn[2:0] = 0)
the timer is stopped. However, the TCNTn value can be accessed by the CPU, regardless of
whether clk
Tn is present or not. A CPU write overrides (has priority over) all counter clear or
count operations.
The counting sequence is determined by the setting of the WGMn1 and WGMn0 bits located in
the Timer/Counter Control Register (TCCRnA) and the WGMn2 bit located in the Timer/Counter
Control Register B (TCCRnB). There are close connections between how the counter behaves
(counts) and how waveforms are generated on the Output Compare output OCnA. For more
details about advanced counting sequences and waveform generation, see “Modes of Opera-
The Timer/Counter Overflow Flag (TOVn) is set according to the mode of operation selected by
the WGMn[1:0] bits. TOVn can be used for generating a CPU interrupt.
12.5
Output Compare Unit
The 8-bit comparator continuously compares TCNTn with the Output Compare Registers
(OCRnA and OCRnB). Whenever TCNTn equals OCRnA or OCRnB, the comparator signals a
match. A match will set the Output Compare Flag (OCFnA or OCFnB) at the next timer clock
cycle. If the corresponding interrupt is enabled, the Output Compare Flag generates an Output
Compare interrupt. The Output Compare Flag is automatically cleared when the interrupt is exe-
cuted. Alternatively, the flag can be cleared by software by writing a logical one to its I/O bit
location. The Waveform Generator uses the match signal to generate an output according to
operating mode set by the WGMn[2:0] bits and Compare Output mode (COMnx[1:0]) bits. The
max and bottom signals are used by the Waveform Generator for handling the special cases of
the extreme values in some modes of operation. See “Modes of Operation” on page 85.
DATA BUS
TCNTn
Control Logic
count
TOVn
(Int.Req.)
Clock Select
top
Tn
Edge
Detector
( From Prescaler )
clk
Tn
bottom
direction
clear
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ATTINY44-15SSZ 功能描述:8位微控制器 -MCU 4KB Flash 15MHz Auto 125-degrees C RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT
ATTINY441-MMH 制造商:Atmel Corporation 功能描述:16MHZ, 3X3MM, 20 VQFN, IND. GRADE, GREEN - Bulk 制造商:Atmel Corporation 功能描述:IC MCU 8BIT 4KB FLASH 20VQFN