参数资料
型号: ATTINY43U-SU
厂商: Atmel
文件页数: 152/158页
文件大小: 0K
描述: MCU AVR 4K FLASH 8MHZ 20-SOIC
产品培训模块: ATtiny43U Overview
MCU Product Line Introduction
tinyAVR Introduction
标准包装: 37
系列: AVR® ATtiny
核心处理器: AVR
芯体尺寸: 8-位
速度: 8MHz
连通性: USI
外围设备: 欠压检测/复位,POR,PWM,温度传感器,WDT
输入/输出数: 16
程序存储器容量: 4KB(2K x 16)
程序存储器类型: 闪存
EEPROM 大小: 64 x 8
RAM 容量: 256 x 8
电压 - 电源 (Vcc/Vdd): 1.8 V ~ 5.5 V
数据转换器: A/D 4x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 20-SOIC(0.295",7.50mm 宽)
包装: 管件
产品目录页面: 613 (CN2011-ZH PDF)
配用: ATSTK600-TINYX3U-ND - STK600 SOCKET/ADAPTER TINYX3U
93
8048C–AVR–02/12
ATtiny43U
Table 12-4 on page 93 shows the COMnA[1:0] bit functionality when the WGMn[2:0] bits are set
to phase correct PWM mode.
Note:
1. A special case occurs when OCRnA equals TOP and COMnA1 is set. In this case, the Com-
pare Match is ignored, but the set or clear is done at TOP. See “Phase Correct PWM Mode” on
page 88 for more details.
Bits 5:4 – COMnB[1:0]: Compare Match Output B Mode
These bits control the Output Compare pin (OCnB) behavior. If one or both of the COMnB[1:0]
bits are set, the OCnB output overrides the normal port functionality of the I/O pin it is connected
to. However, note that the Data Direction Register (DDR) bit corresponding to the OCnB pin
must be set in order to enable the output driver.
When OCnB is connected to the pin, the function of the COMnB[1:0] bits depends on the
WGMn[2:0] bit setting. Table 12-5 on page 93 shows the COMnB[1:0] bit functionality when the
WGMn[2:0] bits are set to a normal or CTC mode (non-PWM).
Table 12-6 on page 93 shows the COMnB[1:0] bit functionality when the WGMn[2:0] bits are set
to fast PWM mode.
Note:
1. A special case occurs when OCRnB equals TOP and COMnB1 is set. In this case, the Com-
pare Match is ignored, but the set or clear is done at TOP. See “Fast PWM Mode” on page 86
for more details.
Table 12-4.
Compare Output Mode, Phase Correct PWM Mode(1)
COMnA1
COMnA0
Description
0
Normal port operation, OCnA disconnected.
01
WGMn2 = 0: Normal Port Operation, OCnA Disconnected.
WGMn2 = 1: Toggle OCnA on Compare Match.
10
Clear OCnA on Compare Match when up-counting. Set OCnA on
Compare Match when down-counting.
11
Set OCnA on Compare Match when up-counting. Clear OCnA on
Compare Match when down-counting.
Table 12-5.
Compare Output Mode, non-PWM Mode
COMnB1
COMnB0
Description
0
Normal port operation, OCnB disconnected.
0
1
Toggle OCnB on Compare Match
1
0
Clear OCnB on Compare Match
1
Set OCnB on Compare Match
Table 12-6.
Compare Output Mode, Fast PWM Mode
COMnB1
COMnB0
Description
0
Normal port operation, OCnB disconnected.
01
Reserved
1
0
Clear OCnB on Compare Match, set OC0B at TOP
1
Set OCnB on Compare Match, clear OC0B at TOP
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