参数资料
型号: ATTINY43U-SUR
厂商: Atmel
文件页数: 154/158页
文件大小: 0K
描述: MCU AVR 4KB FLASH 8MHZ 20SOIC
产品培训模块: tinyAVR Introduction
标准包装: 1,000
系列: AVR® ATtiny
核心处理器: AVR
芯体尺寸: 8-位
速度: 8MHz
连通性: USI
外围设备: 欠压检测/复位,POR,PWM,温度传感器,WDT
输入/输出数: 16
程序存储器容量: 4KB(2K x 16)
程序存储器类型: 闪存
EEPROM 大小: 64 x 8
RAM 容量: 256 x 8
电压 - 电源 (Vcc/Vdd): 1.8 V ~ 5.5 V
数据转换器: A/D 4x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 20-SOIC(0.295",7.50mm 宽)
包装: 带卷 (TR)
其它名称: ATTINY43U-SUR-ND
95
8048C–AVR–02/12
ATtiny43U
12.9.3
TCCR0B – Timer/Counter Control Register B
12.9.4
TCCR1B – Timer/Counter Control Register B
Bit 7 – FOCnA: Force Output Compare A
The FOCnA bit is only active when the WGM bits specify a non-PWM mode.
However, for ensuring compatibility with future devices, this bit must be set to zero when
TCCRnB is written when operating in PWM mode. When writing a logical one to the FOCnA bit,
an immediate Compare Match is forced on the Waveform Generation unit. The OCnA output is
changed according to its COMnA[1:0] bits setting. Note that the FOCnA bit is implemented as a
strobe. Therefore it is the value present in the COMnA[1:0] bits that determines the effect of the
forced compare.
A FOCnA strobe will not generate any interrupt, nor will it clear the timer in CTC mode using
OCRnA as TOP.
The FOCnA bit is always read as zero.
Bit 6 – FOCnB: Force Output Compare B
The FOCnB bit is only active when the WGM bits specify a non-PWM mode.
However, for ensuring compatibility with future devices, this bit must be set to zero when
TCCR0B is written when operating in PWM mode. When writing a logical one to the FOCnB bit,
an immediate Compare Match is forced on the Waveform Generation unit. The OCnB output is
changed according to its COMnB[1:0] bits setting. Note that the FOCnB bit is implemented as a
strobe. Therefore it is the value present in the COMnB[1:0] bits that determines the effect of the
forced compare.
A FOCnB strobe will not generate any interrupt, nor will it clear the timer in CTC mode using
OCRnB as TOP.
The FOCnB bit is always read as zero.
Bits 5:4 – Res: Reserved Bits
These bits are reserved and will always read zero.
Bit 3 – WGMn2: Waveform Generation Mode
See the description in the “Register Description” on page 92.
Bits 2:0 – CSn[2:0]: Clock Select
Bit
7
6
5
4
3
2
1
0
FOC0A
FOC0B
WGM02
CS02
CS01
CS00
TCCR0B
Read/Write
W
R
R/W
Initial Value
0
Bit
7
6
5
4
3
2
1
0
FOC1A
FOC1B
––
WGM12
CS12
CS11
CS10
TCCR1B
Read/Write
W
R
R/W
Initial Value
0
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