参数资料
型号: ATTINY84A-CCU
厂商: Atmel
文件页数: 73/135页
文件大小: 0K
描述: IC MCU 8BIT 8K FLASH 15UFBGA
标准包装: 490
系列: AVR® ATtiny
核心处理器: AVR
芯体尺寸: 8-位
速度: 20MHz
连通性: USI
外围设备: 欠压检测/复位,POR,PWM,温度传感器,WDT
输入/输出数: 12
程序存储器容量: 8KB(4K x 16)
程序存储器类型: 闪存
EEPROM 大小: 512 x 8
RAM 容量: 512 x 8
电压 - 电源 (Vcc/Vdd): 1.8 V ~ 5.5 V
数据转换器: A/D 8x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 15-UFBGA
包装: 托盘
41
8183F–AVR–06/12
ATtiny24A/44A/84A
8.2.4
Watchdog Reset
When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On
the falling edge of this pulse, the delay timer starts counting the Time-out period t
TOUT. See
“Watchdog Timer” on page 41 for details on operation of the Watchdog Timer.
Figure 8-6.
Watchdog Reset During Operation
8.3
Internal Voltage Reference
ATtiny24A/44A/84A features an internal bandgap reference. This reference is used for Brown-
out Detection, and it can be used as an input to the Analog Comparator or the ADC. The band-
gap voltage varies with supply voltage and temperature.
8.3.1
Voltage Reference Enable Signals and Start-up Time
The voltage reference has a start-up time that may influence the way it should be used. The
start-up time is given in “System and Reset Characteristics” on page 176. To save power, the
reference is not always turned on. The reference is on during the following situations:
1.
When the BOD is enabled (by programming the BODLEVEL[2:0] Fuse).
2.
When the internal reference is connected to the Analog Comparator (by setting the
ACBG bit in ACSR).
3.
When the ADC is enabled.
Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC, the user
must always allow the reference to start up before the output from the Analog Comparator or
ADC is used. To reduce power consumption in Power-down mode, the user can avoid the three
conditions above to ensure that the reference is turned off before entering Power-down mode.
8.4
Watchdog Timer
The Watchdog Timer is clocked from an On-chip Oscillator which runs at 128 kHz. By controlling
the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted as shown in Table
8-3 on page 46. The WDR – Watchdog Reset – instruction resets the Watchdog Timer. The
Watchdog Timer is also reset when it is disabled and when a Chip Reset occurs. Ten different
clock cycle periods can be selected to determine the reset period. If the reset period expires
without another Watchdog Reset, the ATtiny24A/44A/84A resets and executes from the Reset
Vector. For timing details on the Watchdog Reset, refer to Table 8-3 on page 46.
CK
CC
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