General Description
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Embedded Memory
As mentioned earlier, each core tile has either three (in a smaller tile) or four (in the regular tile)
embedded SRAM blocks along the west side, and each variable-aspect-ratio SRAM block is 4,608 bits in
size. Available memory configurations are: 128x36, 256x18, 512x9, 1kx4, 2kx2 or 4kx1 bits. The
individual blocks have separate read and write ports that can be configured with different bit widths on
each port. For example, data can be written in by eight and read out by one.
In addition, every SRAM block has an embedded FIFO control unit. The control unit allows the SRAM
block to be configured as a synchronous FIFO without using core logic modules. The FIFO width and
depth are programmable. The FIFO also features programmable ALMOST-EMPTY (AEMPTY) and
ALMOST-FULL (AFULL) flags in addition to the normal EMPTY and FULL flags. In addition to the flag
logic, the embedded FIFO control unit also contains the counters necessary for the generation of the
read and write address pointers as well as control circuitry to prevent metastability and erroneous
operation. The embedded SRAM/FIFO blocks can be cascaded to create larger configurations.
I/O Logic
The Axcelerator family of FPGAs features a flexible I/O structure, supporting a range of mixed voltages
with its bank-selectable I/Os: 1.5V, 1.8V, 2.5V, and 3.3V. In all, Axcelerator FPGAs support at least 14
different I/O standards (single-ended, differential, voltage-referenced). The I/Os are organized into
banks, with eight banks per device (two per side). The configuration of these banks determines the I/O
in each bank.
Each I/O module has an input register (InReg), an output register (OutReg), and an enable register
modules, and a buffer (B) module.
Figure 1-6
AX Device Architecture (AX1000 shown)
Chip Layout
SuperCluster
I/O Structure
See Figure 7
RAMC
HD
SC
HD
SC
HD
SC
HD
SC
HD
SC
HD
SC
HD
SC
RD
SC
HD
SC
HD
SC
HD
SC
HD
SC
HD
SC
HD
SC
Core Tile
4k
RAM/
FIFO
4k
RAM/
FIFO
4k
RAM/
FIFO
4k
RAM/
FIFO
RX
TX
B
C
R
C
R
RX
TX