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| 型号： | AXDA1600DUT3C |
| 厂商： | ADVANCED MICRO DEVICES INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 1400 MHz, MICROPROCESSOR, CPGA453 |
| 封装： | OPGA-453 |
| 文件页数： | 38/106页 |
| 文件大小： | 2275K |
| 代理商： | AXDA1600DUT3C |
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Chapter 6
Advanced 266 Front-Side Bus AMD Athlon XP Processor Model 8 Specifications
25
25175H—March 2003
AMD Athlon XP Processor Model 8 Data Sheet
Preliminary Information
6.3
Advanced 266 FSB AMD Athlon System Bus
AC Characteristics
The AC characteristics for the AMD Athlon system bus of this
processor are shown in Table 4. The parameters are grouped
based on the source or destination of the signals involved.
Table 4.
AMD Athlon System Bus AC Characteristics
Group
Symbol
Parameter
Min
Max
Units
Notes
All Signals
TRISE
Output Rise Slew Rate
1
3
V/ns
1
TFALL
Output Fall Slew Rate
1
3
V/ns
1
Forward
Clocks
TSKEW-SAMEEDGE
Output skew with respect to
the same clock edge
–385
ps
2
TSKEW-DIFFEDGE
Output skew with respect to a
different clock edge
–770
ps
2
TSU
Input Data Setup Time
300
ps
3
THD
Input Data Hold Time
300
ps
3
CIN
Capacitance on input Clocks
4
25
pF
COUT
Capacitance on output Clocks
4
12
pF
Sync
TVAL
RSTCLK to Output Valid
250
2000
ps
4, 5
TSU
Setup to RSTCLK
500
ps
4, 6
THD
Hold from RSTCLK
1000
ps
4, 6
Notes:
1. Rise and fall time ranges are guidelines over which the I/O has been characterized.
2. TSKEW-SAMEEDGE is the maximum skew within a clock forwarded group between any two signals or between any signal and its
forward clock, as measured at the package, with respect to the same clock edge.
TSKEW-DIFFEDGE is the maximum skew within a clock forwarded group between any two signals or between any signal and its
forward clock, as measured at the package, with respect to different clock edges.
3. Input SU and HD times are with respect to the appropriate Clock Forward Group input clock.
4. The synchronous signals include
PROCRDY, CONNECT, and CLKFWDRST.
5. TVAL is RSTCLK rising edge to output valid for PROCRDY. Test Load is 25 pF.
6. TSU is setup of CONNECT/CLKFWDRST to rising edge of RSTCLK. THD is hold of CONNECT/CLKFWDRST from rising edge of
RSTCLK.
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