参数资料
| 型号： | BD6522F-E2 |
| 厂商： | Rohm Semiconductor |
| 文件页数： | 24/31页 |
| 文件大小： | 0K |
| 描述： | IC PWR MANAGEMENT SWITCH SOP8 TR |
| 标准包装： | 2,500 |
| 类型： | 高端开关 |
| 输出数： | 1 |
| Rds（开）： | 70 毫欧 |
| 内部开关： | 是 |
| 电流限制： | 2.0A |
| 输入电压： | 3 V ~ 5.5 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.173"，4.40mm 宽） |
| 供应商设备封装： | 8-SOP |
| 包装： | 带卷 (TR) |
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BD6520F
BD6522F
Datasheet
● Operational Notes
(1) Absolute Maximum Ratings
Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit
between pins or an open circuit between pins. Therefore, it is important to consider circuit protection measures, such as
adding a fuse, in case the IC is operated over the absolute maximum ratings
(2) Recommended operating conditions
These conditions represent a range within which the expected characteristics of the IC can be approximately obtained.
The electrical characteristics are guaranteed under the conditions of each parameter.
(3) Reverse connection of power supply
Connecting the power supply in reverse polarity can damage the IC. Take precautions against reverse polarity when
connecting the power supply, such as mounting an external diode between the power supply and the IC’s power supply
terminals.
(4) Power supply line
Design the PCB layout pattern to provide low impedance ground and supply lines. Separate the ground and supply lines
of the digital and analog blocks to prevent noise in the ground and supply lines of the digital block from affecting the
analog block. Furthermore, connect a capacitor to ground at all power supply pins. Consider the effect of temperature and
aging on the capacitance value when using electrolytic capacitors.
(5) Ground Voltage
The voltage of the ground pin must be the lowest voltage of all pins of the IC at all operating conditions. Ensure that no
pins are at a voltage below the ground pin at any time, even during transient condition.
(6) Short between pins and mounting errors
Be careful when mounting the IC on printed circuit boards. The IC may be damaged if it is mounted in a wrong orientation
or if pins are shorted together. Short circuit may be caused by conductive particles caught between the pins.
(7) Operation under strong electromagnetic field
Operating the IC in the presence of a strong electromagnetic field may cause the IC to malfunction.
(8) Testing on application boards
When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may subject
the IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply should always
be turned off completely before connecting or removing it from the test setup during the inspection process. To prevent
damage from static discharge, ground the IC during assembly and use similar precautions during transport and storage.
(9) ? Regarding input pins of the IC
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated.
P-N junctions are formed at the intersection of the P layers with the N layers of other elements, creating a parasitic diode
or transistor. For example (refer to figure below):
When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.
When GND > Pin B, the P-N junction operates as a parasitic transistor.
Parasitic diodes inevitably occur in the structure of the IC. The operation of parasitic diodes can result in mutual
interference among circuits, operational faults, or physical damage. Therefore, conditions that cause these diodes to
operate, such as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should be
avoided.
Resistor
Transistor (NPN)
Pin A
Pin B
C
B
Pin B
Pin A
E
N
P +
N
P
P +
N
Parasitic
element
N
P +
N
P
P +
N
B
C
E
P substrate
P substrate
Parasitic
Parasitic element
GND
Parasitic element
GND
GND
GND element
Other adjacent elements
Example of monolithic IC structure
www.rohm.com
? 2013 ROHM Co., Ltd. All rights reserved.
TSZ22111 ? 15 ? 001
24/28
TSZ02201-0E3E0H300250-1-2
11.Mar.2013 Rev.001
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