参数资料
型号: BD8132FV-E2
厂商: Rohm Semiconductor
文件页数: 9/23页
文件大小: 0K
描述: IC PWR SUP CORRECTION SSOP-B40
标准包装: 2,000
系列: *
BD8132FV, BD8139AEFV
Technical Note
[BD8132FV]
● Serial communications
The serial data control block consists of a register that stores data from the LATCH, CLK, and SDIN pins, and a DAC circuit
that receives the output from this register and provides adjusted voltages to other IC blocks.
When the IC's power supply is activated, the reset function operates to set the register to a preset value. The first bit is for
testing use only and should always be set to 0. The next bit is used to select the OSC mode. Inputting a value of 0 selects
internal frequency mode and uses a frequency of 80 kHz. Entering a value of 1 selects external frequency mode. Input an
external clock signal from the OSC pin.
Serial data control block diagram
LATCH
CLK
SDIN
Clock control
Shift register
10 bits
5 bits
1 bit
1 bit
OUT0 to OUTI
registers
Address
decoder
OSC
mode
Test
mode
DAC
Fig. 21 Serial Block Diagram
(1) Serial communications timing
The 17-bit serial data input from the SDIN pin is read into the shift register using the rising edge of the signal input to the
CLK pin. This data is then loaded to the DAC register using the rising edge of the signal input to the LATCH pin.
If the data loaded into the shift register while the LATCH pin is low consists of less than 17 bits, the loaded data is
discarded. If the data exceeds 17 bits, the last 17 bits to be loaded are treated as valid.
Serial communications timing
LATCH
CLK
SDIN
d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d1 1 d12 d13 d14 d15 d16
Fig. 22 Serial Communications Timing Chart
(2) Serial data
The following table illustrates the format of serial data input to the SDIN pin.
First →
→ Last
d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10
d11 d12
d13
d14
d15 d16
0 X Register address
Data
Register
Register 0
Register 1
Register 2
Register 3
Register 4
Register 5
Register 6
Register 7
Register 8
Register 9
Register A
Register B
Register C
Register D
Register E
Register F
Register G
Register H
Register I
d2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
d3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
Address
d4
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
d5
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
d6
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Behavior when data increases
V0 voltage value increases
V1 voltage value increases
V2 voltage value increases
V3 voltage value increases
V4 voltage value increases
V5 voltage value increases
V6 voltage value increases
V7 voltage value increases
V8 voltage value increases
V9 voltage value increases
VA voltage value increases
VB voltage value increases
VC voltage value increases
VD voltage value increases
VE voltage value increases
VF voltage value increases
VG voltage value increases
VH voltage value increases
Vcom voltage value increases
Preset value
d7 to d16
00000 00000
00000 00000
00000 00000
00000 00000
00000 00000
00000 00000
00000 00000
00000 00000
00000 00000
00000 00000
00000 00000
00000 00000
00000 00000
00000 00000
00000 00000
00000 00000
00000 00000
00000 00000
00000 00000
www.rohm.com
? 2009 ROHM Co., Ltd. All rights reserved.
9/20
2009.07 - Rev.B
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