参数资料
| 型号： | BD8966FVM-TR |
| 厂商： | Rohm Semiconductor |
| 文件页数： | 14/19页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 0.8A MSOP8 |
| 标准包装： | 3,000 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 1 V ~ 2.5 V |
| 输入电压： | 4 V ~ 5.5 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 1MHz |
| 电流 - 输出： | 800mA |
| 同步整流器： | 是 |
| 工作温度： | -25°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-VSSOP，8-MSOP（0.110"，2.80mm 宽） |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 8-MSOP |
BD8966FVM
Datasheet
Stable feedback loop may be achieved by canceling the pole fp (Min.) produced by the output capacitor and the load
resistance with CR zero correction by the error amplifier.
fz (Amp.) = fp (Min.)
1
2π×R ITH ×C ITH
=
1
2π×R OMax. ×C O
5. Determination of output voltage
The output voltage V OUT is determined by the equation (7):
V OUT =(R2/R1+1)×V ADJ ??? (7) V ADJ : Voltage at ADJ terminal (0.8V Typ.)
With R1 and R2 adjusted, the output voltage may be determined as required.
(Adjustable output voltage range: 1.0V to 2.5V)
Use 1 k? to 100 k? resistor for R1. If a resistor of the resistance higher than
100 k? is used, check the assembled set carefully for ripple voltage etc.
6
1
SW
ADJ
4.7μH
10μF
R2
R1
Output
Fig.31 Determination of output voltage
BD8966FVM Cautions on PC Board Layout
V CC
1
2
ADJ
V CC
EN
PV CC
8
7
EN
3
ITH
SW
6
L
①
V OUT
R ITH
③
C ITH
4
GND
PGND
5
C IN
②
C o
GND
Fig.32 Layout diagram
① For the sections drawn with heavy line, use thick conductor pattern as short as possible.
② Lay out the input ceramic capacitor CIN closer to the pins PVCC and PGND, and the output capacitor Co closer to the
pin PGND.
③ Lay out CITH and RITH between the pins ITH and GND as near as possible with least necessary wiring.
www.rohm.com
? ROHM Co., Ltd. All rights reserved.
TSZ22111 ? 15 ? 001
14/17
TSZ02201-0J3J0AJ00060-1-2
02.MAR.2012. Rev.001
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