参数资料
| 型号： | BD9137MUV-E2 |
| 厂商： | Rohm Semiconductor |
| 文件页数： | 13/21页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 4A 20VQFN |
| 标准包装： | 1 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.8 V ~ 3.3 V |
| 输入电压： | 2.7 V ~ 5.5 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 1MHz |
| 电流 - 输出： | 4A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-VFQFN 裸露焊盘 |
| 包装： | 标准包装 |
| 供应商设备封装： | 20-VQFN |
| 其它名称： | BD9137MUV-E2DKR |
BD9137MUV
3. Selection of input capacitor (Cin)
Datasheet
V CC
Cin
Input capacitor to select must be a low ESR capacitor of the capacitance
sufficient to cope with high ripple current to prevent high transient voltage. The
ripple current IRMS is given by the equation (5):
V CC
2
L
Co
V OUT
√ V OUT (V CC -V OUT )
I RMS =I OUT ×
< Worst case > I RMS(max.)
I OUT
When Vcc=2 × V OUT , I RMS =
[A] ??? (5)
Fig.30 Input capacitor
If V CC =3.3V, V OUT =1.8V, and I OUTmax.= 3A, (BD9137MUV)
I RMS =2 ×
√ 1.8(3.3-1.8)
3 3.3
.
=1.49[A RMS ]
3
A low ESR 22μF/10V ceramic capacitor is recommended to reduce ESR dissipation of input capacitor for better efficiency.
4. Determination of RITH, CITH that works as a phase compensator
As the Current Mode Control is designed to limit a inductor current, a pole (phase lag) appears in the low frequency area
due to a CR filter consisting of a output capacitor and a load resistance, while a zero (phase lead) appears in the high
frequency area due to the output capacitor and its ESR. So, the phases are easily compensated by adding a zero to the
power amplifier output with C and R as described below to cancel a pole at the power amplifier.
fp(Min.)
fp=
fz (ESR) =
Gain
[dB]
A
0
I OUT Min.
fp(Max.)
I OUT Max.
fz(ESR)
1
2 π× R O × C O
1
2 π× E SR × C O
Pole at power amplifier
Phase
[deg]
0
When the output current decreases, the load resistance Ro
increases and the pole frequency lowers.
-90
Fig.31 Open loop gain characteristics
fp (Min.) =
fp (Max.) =
1
2 π× R OMax. × C O
1
2 π× R OMin. × C O
[Hz] ← with lighter load
[Hz] ← with heavier load
fz (Amp.) =
Gain
[dB]
Phase
[deg]
A
0
0
-90
fz(Amp.)
Zero at power amplifier
Increasing capacitance of the output capacitor lowers the
pole frequency while the zero frequency does not change.
(This is because when the capacitance is doubled, the
capacitor ESR reduces to half.)
1
2 π× R ITH × C ITH
Fig.32 Error amp phase compensation characteristics
www.rohm.com
?2012 ROHM Co., Ltd. All rights reserved.
TSZ22111 ? 15 ? 001
13/19
TSZ02201-0J3J0AJ00160-1-2
02.MAR.2012 Rev.001
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