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| 型号： | BD9153MUV-E2 |
| 厂商： | Rohm Semiconductor |
| 文件页数： | 13/21页 |
| 文件大小： | 630K |
| 描述： | IC REG TRPL BCK/LINEAR 24VQFN |
| 特色产品： | CMOS LDO Regulators |
| 标准包装： | 1 |
| 拓扑： | 降压（降压）同步（2），线性（LDO）（1） |
| 功能： | 任何功能 |
| 输出数： | 3 |
| 频率 - 开关： | 1MHz |
| 电压/电流 - 输出 1： | 1.8 V ~ 3.3 V，1.5A |
| 电压/电流 - 输出 2： | 0.8 V ~ 2.5 V，1.5A |
| 电压/电流 - 输出 3： | 控制器 |
| 带 LED 驱动器： | 无 |
| 带监控器： | 无 |
| 带序列发生器： | 无 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-VFQFN 裸露焊盘 |
| 供应商设备封装： | 24-VQFN |
| 包装： | 标准包装 |
| 其它名称： | BD9153MUV-E2DKR |
Technical Note
13/18
www.rohm.com
2009.08 - Rev.A
?2009 ROHM Co., Ltd. All rights reserved.
BD9153MUV
3. Selection of input capacitor (Cin)
A low ESR 22礔/10V ceramic capacitor is recommended to reduce ESR dissipation of input capacitor for better efficiency.
4. Determination of RITH, CITH that works as a phase compensator
As the Current Mode Control is designed to limit a inductor current, a pole (phase lag) appears in the low frequency area
due to a CR filter consisting of a output capacitor and a load resistance, while a zero (phase lead) appears in the high
frequency area due to the output capacitor and its ESR. So, the phases are easily compensated by adding a zero to the
power amplifier output with C and R as described below to cancel a pole at the power amplifier.
Input capacitor to select must be a low ESR capacitor of the capacitance
sufficient to cope with high ripple current to prevent high transient voltage. The
ripple current IRMS is given by the equation (5):
IRMS=IOUT?
VOUTVCC-VOUT
VCC
A?
When Vcc=2譜OUT, IRMS =
IOUT
2
< Worst case > IRMS(max.)
IRMS=2?
1.85.0-1.8
5.0
= 0.48[ARMS]
Gain
[dB]
Phase
[deg]
Fig.38 Open loop gain characteristics
0
0
-90
0
0
-90
fz(Amp.)
Fig.39 Error amp phase compensationcharacteristics
fp=
2雷RO證O
1
fz(ESR)=
2雷ESR證O
1
Pole at power amplifier
When the output current decreases, the load resistance Ro
increases and the pole frequency lowers.
fp(Min.)=
2雷ROMax.證O
1
[Hz]恮ith lighter load
fp(Max.)=
2雷ROMin.證O
1
[Hz] 恮ith heavier load
Zero at power amplifier
fz(Amp.)=
2雷RITH證ITH
1
Fig.37 Input capacitor
fp(Min.)
fp(Max.)
fz(ESR)
IOUTMin.
IOUTMax.
Gain
[dB]
Phase
[deg]
VOUT
VCC
L
Co
Cin
Increasing capacitance of the output capacitor lowers
the pole frequency while the zero frequency does not change.
(This is because when the capacitance is doubled, the
capacitor ESR reduces to half.)
If VCC=5.0V, VOUT=1.8V, and IOUTmax.=1.5A, (BD9153MUV)
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