参数资料
型号: BD9300FV-E2
厂商: Rohm Semiconductor
文件页数: 11/17页
文件大小: 0K
描述: IC REG CTRLR BST INV PWM 14-SSOP
标准包装: 1
PWM 型: 控制器
输出数: 1
频率 - 最大: 800kHz
占空比: 100%
电源电压: 3.6 V ~ 35 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 14-LSSOP(0.173",4.40mm 宽)
包装: 标准包装
产品目录页面: 1373 (CN2011-ZH PDF)
其它名称: BD9300FV-E2DKR
2. For output capacitors having high ESR, such as aluminum electrolytic capacitor
For output capacitors having high ESR (i.e., several ohms), the phase compensation setting procedure becomes
comparatively simple. Since the DC/DC converter application has a LC resonant circuit attached to the output,
a – 180 ? phase-delay occurs in that area. If ESR component is present there, however, a +90 ? phase-lead occurs to shift
the phase delay to – 90 ? . Since the phase delay is desired to set within 150 ? , this is a very effective method but has
a demerit to increase the ripple component of the output voltage.
(3) LC resonant circuit
Vcc
(4) With ESR provided
Vcc
L
C
Vo
L
R ESR
Vo
C
fz=
[Hz]
f z =
[Hz] : Resonance point
At this resonance point, a -180 ?
f ESR =
[Hz] : Phase lead
phase-delay occurs.
A – 90 ? phase-delay occurs.
* Same for the phase compensation of inverting and step-up voltages
Fig. 23 DC/DC converter output application
According to changes in phase characteristics due to the ESR, only one phase lead should be inserted. For this phase
lead, select either of the methods shown below:
(5) Insert feedback resistance in the C.
(6) Insert the R3 in integrator.
Vo
C1
C2
Vo
R3
C2
R1
R1
+
A
FB
+
A
FB
R2
Phase lead: fz=
[Hz]
Phase lead: fz=
[Hz]
Fig. 24 Typical phase compensation circuit
To cancel the LC resonance, phase lead frequency should be set close to the LC resonant frequency.
11/16
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