参数资料
型号: BD9300FV-E2
厂商: Rohm Semiconductor
文件页数: 12/17页
文件大小: 0K
描述: IC REG CTRLR BST INV PWM 14-SSOP
标准包装: 1
PWM 型: 控制器
输出数: 1
频率 - 最大: 800kHz
占空比: 100%
电源电压: 3.6 V ~ 35 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 14-LSSOP(0.173",4.40mm 宽)
包装: 标准包装
产品目录页面: 1373 (CN2011-ZH PDF)
其它名称: BD9300FV-E2DKR
3. For output capacitors having low ESR, such as a ceramic capacitor or OS-CON
In order to use capacitors having low ESR (i.e., several tens of mW), two phase-leads should be inserted so that a
– 180 ? phase-dela y, due to LC resonance, will be compensated. The following section shows a typical phase
compensation procedure.
. Phase compensation with secondary phase lead
Vo
R3
C2
Phase lead: fz 1 =
[Hz]
R1
C1
INV
+
A
FB
Phase lead: fz 2 =
[Hz]
R2
LC resonant frequency: fr=
[Hz]
Fig. 25 Typical circuit after secondary compensation circuit
For the settings of phase lead frequency, insert both of the phase leads close to the LC resonant frequency.
Phase compensation on the BD9300F/FV
For BD9300F/FV, since the error amplifier input is inverted to the normal input, the phase compensation procedure is
slightly different. (The BD9300F/FV returns feedback to the NON pin.)
Vo
R1
R2
Internal REG
2.5V
100k Ω
+
A
100
k Ω
C
The BD9300 returns feedback to the +
side of the error amplifier.
FB
Fig. 26 Typical circuit after phase compensation on BD9300F/FV
The BD9300F/FV feeds back on the + side input and returns the phase compensation on the - side input. Consequently,
resistance of the resistance divider being used to determine the reference voltage has influence on the frequency
characteristics. (The BD9300F/FV has a 1/2 VREF pin to divide resistance by 100 k Ω .)
The following section shows the phase characteristics.
Primary phase delay: fp =
1
100k Ω
2
[Hz], where A is approximately 80 dB.
Phase lead:
fz =
1
100k Ω
[Hz]
2
As a result, inserting a phase compensation capacitor will cause phase lead component. If any further phase lead is
required, add a capacitor in parallel with the R1.
12/16
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