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参数资料
| 型号： | BD9740KN-E2 |
| 厂商： | Rohm Semiconductor |
| 文件页数： | 4/15页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK BST INV SYNC 48UQFN |
| 标准包装： | 2,500 |
| 类型： | 降压（降压），升压（升压），反相 |
| 输出数： | 7 |
| 输入电压： | 1.5 V ~ 10 V |
| 频率 - 开关： | 100kHz ~ 1.2MHz |
| 电流 - 输出： | 30mA |
| 同步整流器： | 是 |
| 工作温度： | -20°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 48-UQFN |
BD9739KN,BD9740KN
Technical Note
(Unless otherwise specified, Ta = 25 ℃ , VBAT = 3 V, VCC = 5 V, RT = 11 k Ω , CT = 180 pF, STB1 to STB7 = 3 V)
Parameter Symbol
Limits
Min. Typ. Max.
Unit
Conditions
[Power on switching block] (BD9739KN)
SWOUT1
SWOUT4
Output voltage V SAT
Leak current I LEAK
Output voltage V SAT
Leak current I LEAK
－
－
－
－
0.1 0.3 V IO = 1 mA
0 5 μA STB = 0 V
0.1 0.3 V IO = 100 μ A
0 5 μA STB = 0 V
SWOUT4,6
Output voltage V SAT
V SWIN6 - 0.3 V SWIN6 - 0.1
－
V
IO = 20 mA
VSWIN = 5 V
Leak current I LEAK
－
0 5 μA STB = 0 V
SWOUT7
Output voltage V SAT
V SWIN7 - 0.3 V SWIN7 - 0.1
－
V
IO = 10 mA
VSWIN = 10 V
Leak current I LEAK
[Soft start block] (BD9740KN)
－
0 5 μA STB = 0 V
Soft start time of CH4
T SS1
1.8 3.6 6.0
mse
c
VCC = PVCC = 5V,
PVCCH = 5.0V
STB 0 → 3 V
Soft start time of CH2, 3
CH2, CH3 soft start
INV4 threshold voltage at start
T SS2
V PG4
1.8
0.72
3.6
0.80
6.0
0.88
mse
c
V
VCC = PVCC = 5V,
STB = 3 V
INV4 = 0 → 1.2 V
VCC = PVCC = 5 V
PVCCH = 5.0 V
[STB1 to STB7]
STB pin control voltage
ON
OFF
V STBH
V STBL
2.0
-0.3
－
－
11
0.3
V
V
STB
STB pin pull-down resistance
R STB
250
400
700
k Ω
STB
[Circuit current]
Standby current 1
(VBAT pin sink current)
Standby current 2
(VCC, PVCC pin sink current)
Circuit current at startup
(VBAT pin sink current)
Circuit current 1
(VBAT pin sink current)
Circuit current 2
(VCC, PVCC pin sink current)
I STB1
I STB2
I ST
I CC1
I CC2
－
－
－
－
－
－
－
30
100
5
5
5
100
300
15
μA
μA
mA
μA
mA
STB1 to STB7 = 0 V
STB1 to STB7 = 0 V
CT = 1.7 V
VCC = 0 V
CT = 1.7 V
CT = 1.7 V
INV = 2.5 V
Note: This IC is not designed to be radiation-resistant.
● PVCCH and PVCCL input voltages
PVCCH
PVCCL
DRAINH
DRAINL
Vo
PGND
Fig. 1 Synchronous Rectification
Channel with Built-In FET
? Synchronous rectification channels with built-in FETs include, N-channel FETs
for both the high-side and low-side configuration. The driver block's power
source is supplied to the PVCCL pin for the low-side and the PVCCH pin for
the high-side. (For the BD9740KN, both sides are supplied to the PVCCH pin.)
In order to turn the FET on, a potential of at least 4 V must be supplied to the
PVCCL pin, and a potential of at least, DRAINH pin voltage + 4 V, must be
supplied to the PVCCH pin.
Note:
? The breakdown voltage for the PVCCL and PVCCH pins is 15 V.
For applications that with voltages exceeding 15 V, add a zener diode, or other
components, to provide overvoltage protection.
? Shorting the DRAINH pin with the ground, while a charge remains in the output
capacitor, may cause unexpected current flow, resulting in damage to the IC.
Add an external protective diode for applications where this possibility exists.
www.rohm.com
? 2010 ROHM Co., Ltd. All rights reserved.
4/14
2010.09 - Rev.A
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