参数资料
| 型号： | BH31RB1WGUT-E2 |
| 厂商： | Rohm Semiconductor |
| 文件页数： | 7/9页 |
| 文件大小： | 0K |
| 描述： | IC REG LDO 3.1V .15A 4-VCSP |
| 标准包装： | 1 |
| 稳压器拓扑结构： | 正，固定式 |
| 输出电压： | 3.1V |
| 输入电压： | 最高 5.5V |
| 电压 - 压降（标准）： | 0.1V @ 100mA |
| 稳压器数量： | 1 |
| 电流 - 输出： | 150mA（最小值） |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 4-WFBGA，CSPBGA |
| 供应商设备封装： | VCSP60N1 |
| 包装： | 标准包装 |
| 产品目录页面： | 1374 (CN2011-ZH PDF) |
| 其它名称： | BH31RB1WGUT-E2DKR |
BH □□ RB1WGUT series
Technical Note
9. GND voltage
The potential of GND pin must be minimum potential in all operating conditions.
10. Back Current
In applications where the IC may be exposed to back current flow, it is recommended to create a path to dissipate this
current by inserting a bypass diode between the VIN and VOUT pins.
Back current
VIN
STBY
GND
OUT
Fig. 30 Example Bypass Diode Connection
11. Testing on application boards
When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to stress.
Always discharge capacitors after each process or step. Always turn the IC's power supply off before connecting it to or
removing it from a jig or fixture during the inspection process. Ground the IC during assembly steps as an antistatic
measure. Use similar precaution when transporting or storing the IC.
12. Regarding Input Pin of the IC (Fig.31)
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated.
P-N junctions are formed at the intersection of these P layers with the N layers of other elements, creating a parasitic diode
or transistor. For example, the relation between each potential is as follows:
When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.
When GND > Pin B, the P-N junction operates as a parasitic transistor.
Parasitic diodes can occur inevitable in the structure of the IC. The operation of parasitic diodes can result in mutual
interference among circuits, operational faults, or physical damage. Accordingly, methods by which parasitic diodes
operate, such as applying a voltage that is lower than the GND (P substrate) voltage to an input pin, should not be used.
Resistor
Transistor (NPN)
Pin A
Pin B
C
B
Pin B
Pin A
E
N
P +
N
P
P +
N
P substrate
Parasitic
element
N
P +
N
P
P +
N
P substrate
B
C
E
Parasitic
element
Parasitic element
GND
Parasitic element
GND
GND
GND
Other adjacent elements
Fig. 31 Example of IC structure
www.rohm.com
? 2011 ROHM Co., Ltd. All rights reserved.
7/8
2011.01 - Rev.C
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