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参数资料
| 型号： | BQ26221PWR |
| 厂商： | Texas Instruments |
| 文件页数： | 16/23页 |
| 文件大小： | 0K |
| 描述： | IC BATTERY MONITOR HP 8-TSSOP |
| 标准包装： | 1 |
| 功能： | 电池监控器 |
| 电池化学： | 多化学 |
| 电源电压： | 2.8 V ~ 4.5 V |
| 工作温度： | -20°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 8-TSSOP |
| 包装： | 标准包装 |
| 产品目录页面： | 1020 (CN2011-ZH PDF) |
| 其它名称： | 296-17161-6 |
bq26221
SLUS607 ? MAY 2004
APPLICATION INFORMATION
discharge time count registers (DTCH/DTCL)
The DTCH high-byte register (address = 0x68) and the DTCL low-byte register (address = 0x67) determine the
length of time the V SR < V SS indicating a discharge. The counts in these registers are incremented at a rate of
4096 counts per hour. If the DTCH/DTCL register continues to count beyond FFFFH, the STD bit is set in the
MODE/WOE register, indicating a rollover. Once set, DTCH and DTCL increment at a rate of 16 counts per hour.
Note: If a second rollover occurs, STD is cleared. Access to the bq26221 should be timed to clear DTCH/DTCL
more often than every 170 days. The CLR register forces the reset of both the DTCH and DTCL to zero.
charge-time count registers (CTCH/CTCL)
The CTCH high-byte register (address = 0x66) and the CTCL low-byte register (address = 0x65) determine the
length of time the V SR >V SS , indicating a charge activity. The counts in these registers are incremented at a rate
of 4096 counts per hour. If the CTCH/CTCL registers continue to count beyond FFFFH, the STC bit is set in the
MODE/WOE register indicating a rollover. Once set, DTCH and DTCL increment at a rate of 16 counts per hour.
Note: If a second rollover occurs, STC is cleared. Access to the bq26221 should be timed to clear CTCH/CTCL
more often than every 170 days. The CLR register forces the reset of both the CTCH and CTCL to zero.
mode register (MODE)
The MODE register (address 0x64) contains the GPIEN, STAT, STC, STD, POR and wake-up enable
information as described in Table 9.
Table 9. MODE Register Values
MODE BITS
7
6
5
4
3
2
1
0
(MSB)
(LSB)
GPIEN
STAT
STC
STD
WOE2
WOE1
WOE0
POR
Table 10. MODE Register Definitions
16
GPIEN
STAT
STC & STD
WOE[2.0]
POR
GPIEN bit (bit 7) sets the state of the GPIO pin. A 1 configures the GPIO pin as input, while a 0 configures the
GPIO pin as open-drain output. This bit is set to 0 on power-on-reset.
STAT bit (bit 6) sets the state of the open drain output of the GPIO pin (when configured as output by bit 7). A 1
turns off the open drain output while a 0 turns the output on. This bit is set to 1 on power-on-reset.
The slow time charge (STC) and slow time discharge (STD) flags indicate if the CTC or DTC registers have
rolled over beyond FFFFH. STC set to 1 indicates a CTC rollover; STD set to 1 indicates a DTC rollover.
The wake-up output enable (WOE) bits (bits 3, 2 and 1) indicate the voltage level required between SRP and
SRN so that the bq26221 enters sleep mode after a power down command is issued. Whenever |VSRP ? VSRN|
< VWOE, the bq26221 enters sleep mode after the power down command has been issued. On bq26221
power-on-reset these bits are set to 1. Setting all of these bits to zero is valid, but result in immediate sleep.
Refer to Table 3 for the various WOE values.
POR bit (bit 0) indicates a power-on-reset has occurred. This bit is set when VCC has gone below the POR
level. This bit can be also set and cleared by the host, but has no functionality if set by host.
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