参数资料
型号: BQ78PL116EVM
厂商: Texas Instruments
文件页数: 5/35页
文件大小: 0K
描述: EVAL MODULE FOR BQ78PL116
标准包装: 1
系列: *
其它名称: 296-30796
BQ78PL116EVM-ND
SLUSAB8B – OCTOBER 2010 – REVISED FEBRUARY 2011
bq78PL116 TERMINAL FUNCTIONS (continued)
NAME
FIELD
LED1/SEG1
LED2/SEG2
LED3/SEG3
LED4/SEG4
LED5/SEG5
N/C
N/C
OSCI
OSCO
P1N
P2N
P2S
P3N
P3S
P4N
P4S
P-LAN
PRE
PSH/BP/TP
RSTN
SDI1
SDI3
SDO0
SDO2
SMBCLK
SMBDAT
SPROT
V1
V2
V3
V4
VLDO1
VLDO2
VSS
XT1
XT2
XT3
XT4
NO.
29
32
33
34
35
36
26, 27
28
11
12
15
17
16
21
20
23
22
24
3
31
25
14
19
13
18
37
38
30
47
44
42
39
8
43
48
46
45
41
40
TYPE
O
O
O
O
O
O
IO
O
I
O
O
O
O
O
O
O
O
IO
O
IO
I
I
I
O
O
IO
IO
O
IA
IA
IA
IA
P
P
IA
IA
IA
IA
IA
P
(1)
DESCRIPTION
EPD field segment
LED1 – open-drain, active-low, LCD and EPD segment 1
LED2 – open-drain, active-low, LCD and EPD segment 2
LED3 – open-drain, active-low, LCD and EPD segment 3
LED4 – open-drain, active-low, LCD and EPD segment 4
LED5 – open-drain, active-low, LCD and EPD segment 5
Connect 1-M ? resistor to VSS
No connect
External oscillator input (no connect, internal oscillator used)
External oscillator output (no connect, internal oscillator used)
Charge-balance gate drive, cell 1 north
Charge-balance gate drive, cell 2 north
Charge-balance gate drive, cell 2 south
Charge-balance gate drive, cell 3 north
Charge-balance gate drive, cell 3 south
Charge-balance gate drive, cell 4 north
Charge-balance gate drive, cell 4 south
PowerLAN I/O to external bq76PL102 nodes
Precharge MOSFET control (active-high)
Pushbutton detect for LED display, LCD backplane, EPD top plane and charge pump
Device reset, active-low
Connect to SDO0 via a capacitor
Internal PowerLAN connection – connect to SDO2 through a 0.01- μ F capacitor
Requires 100-k ? pullup resistor to VLDO1
Internal PowerLAN connection – connect to SDI3 through a 0.01- μ F capacitor
SMBus clock signal
SMBus data signal
Secondary protection output, active-high (FUSE)
Cell-1 positive input
Cell-2 positive input
Cell-3 positive input
Cell-4 positive input
Internal LDO-1 output, bypass with 10- μ F capacitor to VSS
Internal LDO-2 output, bypass with 10- μ F capacitor to V2
Cell-1 negative input
External temperature-sensor-1 input
External temperature-sensor-2 input
External temperature-sensor-3 input
External temperature-sensor-4 input
Thermal pad. Connect to VSS
? 2010 – 2011, Texas Instruments Incorporated
Product Folder Link(s): bq78PL116
5
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