参数资料
型号: BQ78PL116EVM
厂商: Texas Instruments
文件页数: 9/35页
文件大小: 0K
描述: EVAL MODULE FOR BQ78PL116
标准包装: 1
系列: *
其它名称: 296-30796
BQ78PL116EVM-ND

SMBus Characteristics (1)
over free-air temperature range (unles s otherwise noted)
SLUSAB8B – OCTOBER 2010 – REVISED FEBRUARY 2011
V IL
V IH
PARAMETER
Input low voltage
Input high voltage
TEST CONDITIONS
MIN
0
2.1
TYP
MAX
0.8
5.5
UNIT
V
V
V OL
C L
Output low voltage
Capacitance, each I/O pin
350- μ A sink current
0
0.4
10
V
pF
f SCL
R PU (2)
SCLK nominal clock
frequency
Pullup resistors for SCLK,
SDATA
T A = 25 ° C
V BUS 5 V nominal
V BUS 3 V nominal
10
13.3
2.4
100
100
45.3
6.8
kHz
k Ω
(1)
(2)
SMBus timing and signals meet the SMBus 2.0 specification requirements under normal operating conditions. All signals are measured
with respect to PACK-negative.
Pullups are typically implemented external to the battery pack and are selected to meet SMBus requirements.
PowerLAN Characteristics (1) (2) (3)
over free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
C L
V IH
V OH
V IL
V OL
t r(I)
t f(I)
Load capacitance
Input logic high
Output logic high
Input logic low
Output logic low
Input rise time
Input fall time
SDI1, SDI3, SDO0, SDO2, P-LAN
SDI1
SDI3
SDO0, SDO2
P-LAN
SDI1
SDI3
SDO0, SDO2
P-LAN
SDI1, SDI3
SDI1, SDI3
0.8 VLDO1
0.8 VLDO2
0.9 VLDO1
0.9 VLDO2
100
0.2 VLDO1
0.2 VLDO2
0.1 VLDO1
0.1 VLDO2
500
500
pF
V
V
V
V
ns
ns
t r(O)
t f(O)
Output rise time
Output fall time
SDO0, SDO2, P-LAN
SDO0, SDO2, P-LAN
30
30
50
50
ns
ns
(1)
(2)
(3)
Values specified by design and are over the full input voltage range and the maximum load capacitance.
The SDI and SDO pins are ac-coupled from the cell circuits downstream and upstream, respectively. The limits specified here are the
voltage transitions which must occur within the SDI and SDO rise-and fall-time specifications.
Coupling capacitor between PowerLAN pins is 1000 pF. This value is specified by design.
? 2010 – 2011, Texas Instruments Incorporated
Product Folder Link(s): bq78PL116
9
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