参数资料
型号: BR24C21F-E2
厂商: Rohm Semiconductor
文件页数: 6/21页
文件大小: 0K
描述: IC EEPROM 1KBIT 400KHZ 8SOP
标准包装: 2,500
格式 - 存储器: EEPROMs - 串行
存储器类型: EEPROM
存储容量: 1K (128 x 8)
速度: 400kHz
接口: I²C,2 线串口
电源电压: 2.5 V ~ 5.5 V
工作温度: -40°C ~ 85°C
封装/外壳: 8-SOIC(0.173",4.40mm 宽)
供应商设备封装: 8-SOP
包装: 带卷 (TR)
BR24C21xxx Series (1K)
Datasheet
● Bidirectional mode command
○ Byte Write
When the Master generates a STOP condition, the BR24C21/F/FJ/FV begins the internal write cycle to the nonvolatile array.
S
T
A
R
T
SLAVE
ADDRESS
W
R
I
T
E
WORD
ADDRESS
DATA
S
T
O
P
SDA
LINE
1 0 1 0 * *
*
WA
* 6
WA
0
D7
D0
R A
A
A
/
C
C
C
VCLK
W K
K
K
*:Don ’t care
Figure 8. Byte Write Cycle Timing
○ Page Write
If the Master transmits the next data instead of generating a STOP condition during the byte write cycle, the
BR24C21/F/FJ/FV transfers from byte write function to page write function. After receipt of each word, the three lower
order address bits are internally incremented by one, while the high order four bits of the word address remains constant.
If the master transmits more than eight words, prior to generating the STOP condition, the address counter will “roll over,”
and the previous transmitted data will be overwritten.
S
W
T
R
S
A
R
T
SLAVE
ADDRESS
I
T
E
WORD
ADDRESS
( )
DATA(n)
DATA(n+7)
T
O
P
SDA
LINE
1 0 1 0 * * *
WA
* 6
WA
0
D7
D0
D0
R A
/ C
W K
A
C
K
A
C
K
A
C
K
VCLK
*:Don’t c are
Figure 9. Page Write Cycle Timing
○ Current Read
The BR24C21/F/FJ/FV contains an internal address counter which maintains the address of the last word accessed,
incremented by one. If the last accessed address is address “n” in a Read operation, the next Read operation will access
data from address “n+1” and increment the current address counter. If the last accessed address is address
”n” in a Write operation, the next Read operation will access data from address “n”. If the Master does not transfer an
Acknowledge, but does generate a STOP condition, the current address read operation will only provide a single byte of
data.
At this point, the device discontinues transmission.
(See Figure 12 Sequential Read Cycle Timing)
S
T
A
R
T
SLAVE
ADRESS
R
E
A
D
DATA
S
T
O
P
SDA
LINE
1 0 1 0 * * *
A
R
C
/
W K
D7
D0
*:Don ’ t care
A
C
K
Figure 10. Current Read Cycle Timing
www.rohm.com
? 2012 ROHM Co., Ltd. All rights reserved.
TSZ22111 ? 15 ? 001
6/18
TSZ02201-0R2R0G100270-1-2
10.Jul.2012 Rev.001
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