参数资料
| 型号： | BR24S64FJ-WE2 |
| 厂商： | Rohm Semiconductor |
| 文件页数： | 31/41页 |
| 文件大小： | 0K |
| 描述： | IC EEPROM 64KBIT 400KHZ 8SOP |
| 标准包装： | 1 |
| 格式 - 存储器： | EEPROMs - 串行 |
| 存储器类型： | EEPROM |
| 存储容量： | 64K (8K x 8) |
| 速度： | 400kHz |
| 接口： | I²C，2 线串口 |
| 电源电压： | 1.7 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOP-J |
| 包装： | 标准包装 |
| 产品目录页面： | 1379 (CN2011-ZH PDF) |
| 其它名称： | BR24S64FJ-WE2DKR |
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BR24L □□ -W Series,BR24S □□□ -W Series
Technical Note
● Read Command
○ Read cycle
Data of EEPROM is read. In read cycle, there are random read cycle and current read cycle.
Random read cycle is a command to read data by designating address, and is used generally.
Current read cycle is a command to read data of internal address register without designating address, and is used when
to verify just after write cycle. In both the read cycles, sequential read cycle is available, and the next address data can
be read in succession.
S
T
A
R
T
SLAVE
ADDRESS
W
R
I
T
E
W ORD
A D D R E S S (n)
S
T
A
R
T
S LA V E
ADDRESS
R
E
A
D
D A TA (n)
S
T
O
P
It is necessary to input 'H'
to the last ACK.
SDA
L IN E
1 0 1 0 A 2 A 1 A 0
N o te)
R A
/ C
W K
WA
7
WA
0
A
C
K
1 0 1 0 A 2 A 1 A 0
R A
/ C
W K
D7
D0
A
C
K
Fig.40 Random read cycle (BR24S08/16-W)
S
T
A
R
T
SLAVE
ADDRESS
W
R
I
T
E
1st WORD
ADDRESS（ｎ）
2nd WORD
ADDRESS（ｎ）
S
T
A
R
T
SLAVE
ADDRESS
R
E
A
D
DATA(n)
S
T
O
P
SDA
LINE
1 0 1 0 A2 A1 A0
＊
WA WA WA WA
14 13 12 11
WA
0
1 0 1 0 A2A1 A0
D7
D0
*1
As for WA12, BR24S32-W become Don't care.
As for WA13, BR24S32/64-W become Don't care.
As for WA14, BR24S32/64/128-W become Don't care.
Note )
R A
/ C
W K
*1
A
C
K
A
C
K
R A
/ C
W K
A
C
K
Fig.41 Random read cycle (BR24S32/64/128/256-W)
S
T
A
R
T
S LA V E
ADDRESS
R
E
A
D
D A TA (n )
S
T
O
P
It is necessary to input 'H'
to the last ACK.
SDA
L IN E
1 0 1 0 A 2 A 1 A 0
N ote )
R A
/ C
W K
D7
D0
A
C
K
Fig.42 Current read cycle
SDA
LINE
S
T
A
R
T
SLAVE
ADDRESS
1 0 1 0 A2 A1 A0
Note ）
R
E
A
D
R A
/ C
W K
D7
DATA(n)
D0
A
C
K
A
C
K
D7
DATA(n+x)
D0
A
C
K
S
T
O
P
Fig.43 Sequential read cycle (in the case of current read cycle)
? In random read cycle, data of designated word address can be read.
? When the command just before current read cycle is random read cycle, current read cycle (each including sequential read
cycle), data of incremented last read address (n)-th address, i.e., data of the (n+1)-th address is output.
? When ACK signal 'LOW' after D0 is detected, and stop condition is not sent from master ( μ -COM) side, the next address
data can be read in succession.
? Read cycle is ended by stop condition where 'H' is input to ACK signal after D0 and SDA signal is started at SCL signal 'H'.
? When 'H' is not input to ACK signal after D0, sequential read gets in, and the next data is output.
Therefore, read command cycle cannot be ended. When to end read command cycle, be sure input stop condition to input
'H' to ACK signal after D0, and to start SDA at SCL signal 'H'.
? Sequential read is ended by stop condition where 'H' is input to ACK signal after arbitrary D0 and SDA is started at SCL
signal 'H'.
Note)
*1 *2 *3
1 0 1 0 A2 A1 A0
*1
*2
*3
BR24S16-W A2 becomes P2.
BR24S08/16-W A1 becomes P1.
BR24S08/16-W A0 becomes P0.
Fig.44 Difference of slave address of each type
www.rohm.com
? 2009 ROHM Co., Ltd. All rights reserved.
31/40
2009.09 - Rev.D
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