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参数资料
| 型号： | BR25L020FV-WE2 |
| 厂商： | Rohm Semiconductor |
| 文件页数： | 10/17页 |
| 文件大小： | 0K |
| 描述： | IC EEPROM SER 2KB SPI BUS 8SSOP |
| 标准包装： | 2,500 |
| 格式 - 存储器： | EEPROMs - 串行 |
| 存储器类型： | EEPROM |
| 存储容量： | 2K (256 x 8) |
| 速度： | 5MHz |
| 接口： | SPI 3 线串行 |
| 电源电压： | 1.8 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 8-SSOP 1 型（0.173"，4.4mm 宽） |
| 供应商设备封装： | SSOP-8B |
| 包装： | 带卷 (TR) |
BR25L010-W, BR25L020-W, BR25L040-W, BR25L080-W, BR25L160-W, BR25L320-W, BR25L640-W
Technical Note
At standby
Current at standby
Set CS "H", and be sure to set SCK, SI, WP, HOLD input "L" or "H". Do not input intermediate electric potential.
Timing
As shown in Fig. 45, at standby, when SCK is "H", even if CS is fallen, SI status is not read at fall edge. SI status is read
at SCK rise edge after fall of CS. At standby and at power ON/OFF, set CS "H" status.
Even if CS is fallen at SCL = SI = "H",
SI status is not read at that edge.
CS
Command start here. SI is read.
SCK
0
1
2
SI
Fig.45 Operating timing
WP cancel valid area
WP is normally fixed to "H" or "L" for use, but when WP is controlled so as to cancel write status register command and write
command, pay attention to the following WP valid timing.
While write or write status register command is executed, by setting WP = "L" in cancel valid area, command can be
cancelled. The area from command ope code before CS rise at internal automatic write start becomes the cancel valid area.
However, once write is started, any input cannot be cancelled. WP input becomes Don't Care, and cancellation becomes
invalid.
SCK
CS
15
16
Ope code
WP cancel invalid area
Data
WP cancel invalid area
tE/W
data write time
WP cancel invalid area
invalid
Fig.46 WP valid timing (WRSR)
Ope code
Address
Data
tE/W
data write time
WP cancel invalid area
invalid
WP cancel invalid area
valid
WP cancel invalid area
Fig.47 WP valid timing (WRITE)
HOLD pin
By HOLD pin, command communication can be stopped temporarily. (HOLD status) The HOLD pin carries out command
communications normally when it is HIGH. To get in HOLD status, at command communication, when SCK = LOW, set
the HOLD pin LOW. At HOLD status, SCK and SI become Don't Care, and SO becomes high impedance (High-Z). To
release the HOLD status, set the HOLD pin HIGH when SCK = LOW. After that, communication can be restarted from the
point before the HOLD status. For example, when HOLD status is made after A5 address input at read, after release of
HOLD status, by starting A4 address input, read can be restarted. When in HOLD status, leave CS LOW. When it is set
CS = HIGH in HOLD status, the IC is reset, therefore communication after that cannot be restarted.
www.rohm.com
? 2010 ROHM Co., Ltd. All rights reserved.
10/16
2010.07 - Rev. B
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相关代理商/技术参数 |
参数描述 |
|---|---|
| BR25L020F-W | 制造商:ROHM 制造商全称:Rohm 功能描述:SPI BUS 2Kbit (256 x 8bit) EEPROM |
| BR25L020FWE2 | 制造商:ROHM Semiconductor 功能描述:EEPROM,SPI BUS,2kb,x8,SOP8 |
| BR25L020F-WE2 | 功能描述:电可擦除可编程只读存储器 SPI 2K BIT RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 |
| BR25L020-W | 制造商:ROHM 制造商全称:Rohm 功能描述:SPI BUS Serial EEPROMs |
| BR25L040FJ-W | 制造商:ROHM 制造商全称:Rohm 功能描述:SPI BUS 4Kbit (512 x 8bit) EEPROM |
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