参数资料
型号: BR93L46FVT-WE2
厂商: Rohm Semiconductor
文件页数: 29/41页
文件大小: 0K
描述: IC EEPROM 1KBIT 2MHZ 8TSSOP
标准包装: 1
格式 - 存储器: EEPROMs - 串行
存储器类型: EEPROM
存储容量: 1K (64 x 16)
速度: 2MHz
接口: Microwire 3 线串行
电源电压: 1.8 V ~ 5.5 V
工作温度: -40°C ~ 85°C
封装/外壳: 8-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 8-TSSOP-B
包装: 标准包装
产品目录页面: 1380 (CN2011-ZH PDF)
其它名称: BR93L46FVT-WE2DKR
BR93L -W Series, 93A □□ -WM Series, BR93H □□ -WC Series
● Timing chart
Technical Note
1) Read cycle (READ)
~ ~
~ ~
~ ~
CS
*1
~ ~
SK
1
2
4
~ ~
n
n+1
~ ~
~ ~
BR93H56/66-WC : n=27, m=7
DI
1
1
0
Am
~ ~
A1
A0
BR93H76/86-WC : n=29, m=9
~ ~
*2
~ ~
DO
High-Z
~ ~
0
D15
D14
~ ~
D1
D0
D15 D14
~ ~
*2 The following address data output
( auto increment function )
*1 Start bit
When data “1” is input for the first time after the rise of CS, this is recognized as a start bit. And when “1” is input after plural “0” are input, it is recognized as a
start bit, and the following operation is started. This is common to all the commands to described hereafter .
Fig. 30 Read cycle
○ When the read command is recognized, input address data (16bit) is output to serial. And at that moment, at taking A0, in
sync with the rise of SK, “0” (dummy bit) is output. And, the following data is output in sync with the rise of SK.
This IC has address auto increment function valid only at read command. This is the function where after the above read
execution, by continuously inputting SK clock, the above address data is read sequentially. And, during the auto increment,
keep CS at “H”.
2) Write cycle (WRITE)
CS
~~
~~
~~
~~
tCS
~~
~~
STATUS
SK
1
2
4
~~
~~
n
~~
BR93H56/66-WC : n=27, m=7
BR93H76/86-WC : n=29, m=9
DI
1
0
1
Am
~~
A1
A0
D15
D14
~~
D1
D0
~~
tSV
DO
High-Z
Fig. 31 Write cycle
BUSY
~~
tE/W
READY
In this command, input 16bit data (D15~D0) are written to designated addresses (Am~A0). The actual write starts by the fall
of CS of D0 taken SK clock(n-th clock from the start bit input), to the rise of the (n+1)-th clock.
When STATUS is not detected, (CS="L" fixed) Max. 10ms(Max.5ms:BR93H66RFVM-WC) in conformity with tE/W, and
when STATUS is detected (CS="H"), all commands are not accepted for areas where "L" (BUSY) is output from D0,
therefore, do not input any command.
Write is not made even if CS is started after input of clock after (n+1)-th clocks.
Note) Take tSKH or more from the rise of the n-th clock to the fall of CS.
3) Write all cycyle (WRAL)
CS
tCS
STATUS
SK
1
2
5
m
n
BR93H56/66-WC : n=27, m=9
BR93H76/86-WC : n=29, m=11
DI
1
0
0
0
1
B2
B1
B0
D15
D1
D0
tSV
DO
High-Z
Fig. 32 Write all cycle
BUSY
tE/W
READY
In this command, input 16bit data is written simultaneously to designated block for 128 words. Data is writen in bulk at a
write time of only Max. 10ms(Max.5ms:BR93H66RFVM-WC) in conformity with tE/W. When writing data to all addresses,
designate each block by B2, B1, and B0, and execute write. Write time is Max.10ms(Max.5ms:BR93H66RFVM-WC). The
actual write starts by the fall of CS from the rise of D0 taken at SK clock (n-th clock from the start bit input), to the rise of the
(n+1)-th clock. When CS is ended after clock input after the rise of the (n+1)-th clock, command is cancelled, and write is
not completed.
Note)Take tSKH or more from the rise of the n-th clock to the fall of CS.
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29/40
2011.09 - Rev.G
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