参数资料
型号: BR93L86RFV-WE2
厂商: Rohm Semiconductor
文件页数: 12/41页
文件大小: 0K
描述: IC EEPROM 16KBIT 2MHZ 8SSOP
标准包装: 1
格式 - 存储器: EEPROMs - 串行
存储器类型: EEPROM
存储容量: 16K (1K x 16)
速度: 2MHz
接口: Microwire 3 线串行
电源电压: 1.8 V ~ 5.5 V
工作温度: -40°C ~ 85°C
封装/外壳: 8-LSSOP(0.173",4.40mm 宽)
供应商设备封装: 8-SSOPB
包装: 标准包装
产品目录页面: 1380 (CN2011-ZH PDF)
其它名称: BR93L86RFV-WE2DKR
BR93L -W Series, 93A □□ -WM Series, BR93H □□ -WC Series
● Timing chart
1) Read cycle (READ)
Technical Note
CS
*1
~ ~
~ ~
~ ~
~ ~
SK
1
2
4
~ ~
~ ~
n
n+1
~ ~
BR93L46-W/A46-WM : n=25, m=5
BR93L56-W/A56-WM
: n=27, m=7
BR93L66-W/A66-WM
DI
1
1
0
Am
~ ~
A1
A0
~ ~
*2
~ ~
BR93L76-W/A76-WM
BR93L86-W/A86-WM
: n=29, m=9
DO
~ ~
0
D15
D14
~ ~
D1
D0
D15 D14
~ ~
High-Z
*1 Start bit
When data “1” is input for the first time after the rise of CS, this is recognized as a start bit. And when “1” is input after plural “0” are input, it is recognized as a
start bit, and the following operation is started. This is common to all the commands to described hereafter.
Fig. 60 Read cycle
○ When the read command is recognized, input address data (16bit) is output to serial. And at that moment, at taking A0, in
sync with the rise of SK, “0” (dummy bit) is output. And, the following data is output in sync with the rise of SK.
This IC has an address auto increment function valid only at read command. This is the function where after the above read
execution, by continuously inputting SK clock, the above address data is read sequentially. And, during the auto increment,
keep CS at “H”.
2) Write cycle (WRITE)
CS
~ ~
~ ~
~ ~
~ ~
tCS
~ ~
~ ~
STATUS
SK
1
2
4
~ ~
~ ~
n
~ ~
BR93L46-W/A46-WM : n=25, m=5
BR93L56-W/A56-WM
: n=27, m=7
BR93L66-W/A66-WM
DI
1
0
1
Am
~ ~
A1
A0
D15
D14
~ ~
D1
D0
~ ~
tSV
BR93L76-W/A76-WM
BR93L86-W/A86-WM
: n=29, m=9
DO
~ ~
BUSY READY
High-Z
tE/W
Fig.61 Write cycle
In this command, input 16bit data (D15~D0) are written to designated addresses (Am~A0). The actual write starts by the fall
of CS of D0 taken SK clock.
When STATUS is not detected, (CS=”L” fixed) Max. 5 ms in conformity with tE/W, and when STATUS is detected (CS=”H”),
all commands are not accepted for areas where “L” (BUSY) is output from D0, therefore, do not input any command.
3) Write all cycyle (WRAL)
CS
~ ~
~ ~
~ ~
~ ~
tCS
~ ~
~ ~
STATUS
SK
1
2
5
n
~ ~
BR93L46-W/A46-WM : n=25
DI
1
0
0
0
1
~ ~
~ ~
~ ~
D15
D14
~ ~
~ ~
~ ~
D1
D0
~ ~
tSV
BR93L56-W/A56-WM
BR93L66-W/A66-WM
BR93L76-W/A76-WM
BR93L86-W/A86-WM
: n=27
: n=29
DO
High-Z
~ ~
BUSY READY
Fig.62 Write all cycle
tE/W
In this command, input 16bit data is written simultaneously to all adresses. Data is not written continuously per one word
but is written in bulk, the write time is only Max. 5ms in conformity with tE/W.
www.rohm.com
? 2011 ROHM Co., Ltd. All rights reserved.
12/40
2011.09 - Rev.G
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