参数资料
型号: BR93L86RFV-WE2
厂商: Rohm Semiconductor
文件页数: 13/41页
文件大小: 0K
描述: IC EEPROM 16KBIT 2MHZ 8SSOP
标准包装: 1
格式 - 存储器: EEPROMs - 串行
存储器类型: EEPROM
存储容量: 16K (1K x 16)
速度: 2MHz
接口: Microwire 3 线串行
电源电压: 1.8 V ~ 5.5 V
工作温度: -40°C ~ 85°C
封装/外壳: 8-LSSOP(0.173",4.40mm 宽)
供应商设备封装: 8-SSOPB
包装: 标准包装
产品目录页面: 1380 (CN2011-ZH PDF)
其它名称: BR93L86RFV-WE2DKR
BR93L -W Series, 93A □□ -WM Series, BR93H □□ -WC Series
4) Write enable (WEN) / disable (WDS) cycle
~ ~
CS
Technical Note
SK
1
2
3
4
5
6
7
8
~ ~
n
BR93L46- W /A46-WM : n=9
DI
1
0
0
ENABLE=1 1
DISABLE=0 0
~ ~
~ ~
BR93L56-W/A56-WM
BR93L66-W/A66-WM
BR93L76-W/A76-WM
BR93L86-W/A86-WM
: n=11
: n=13
DO
High-Z
Fig.63 Write enable (WEN) / disable (WDS) cycle
○ At power on, this IC is in write disable status by the internal RESET circuit. Before executing the write command, it is
necessary to execute the write enable command. And, once this command is executed, it is valid unitl the write disable
command is executed or the power is turned off. However, the read command is valid irrespective of write enable / diable
command. Input to SK after 6 clocks of this command is available by either “H” or “L”, but be sure to input it.
○ When the write enable command is executed after power on, write enable status gets in. When the write disable command
is executed then, the IC gets in write disable status as same as at power on, and then the write command is canceled
thereafter in software manner. However, the read command is executable. In write enable status, even when the write
command is input by mistake, write is started. To prevent such a mistake, it is recommended to execute the write disable
command after completion of write.
5) Erase cycle timing (ERASE)
~ ~
~ ~
CS
tCS
STATUS
~ ~
~ ~
~ ~
~ ~
BR93L46-W/A46-WM : n=9, m=5
SK
DI
1
1
1
2
1
4
Am
~ ~
~ ~
A3
A2
A1
n
A0
~ ~
~ ~
~ ~
~ ~
BR93L56-W/A56-WM
BR93L66-W/A66-WM
BR93L76-W/A76-WM
BR93L86-W/A86-WM
: n=11, m=7
: n=13, m=9
~ ~
tSV
~ ~
BUSY READY
DO
High-Z
~ ~
tE/W
Fig.64 Erase cycle timing
In this command, data of the designated address is made into “1”. The data of the designated address becomes “FFFFh”.
Actual ERASE starts at the fall of CS after the fall of A0 taken SK clock.
In ERASE, status can be detected in the same manner as in WRITE command.
6) Chip erase cycle timing (ERAL)
~ ~
~ ~
CS
tCS
~ ~
STATUS
~ ~
~ ~
BR93L46-W/A46-WM : n=9
SK
1
2
4
~ ~
n
~ ~
~ ~
BR93L56-W/A56-WM
BR93L66-W/A66-WM
: n=11
DI
1
0
0
1
0
~ ~
~ ~
BR93L76-W/A76-WM
BR93L86-W/A86-WM
: n=13
tSV
~ ~
BUSY READY
DO
High-Z
~ ~
tE/W
Fig.65 Chip erase cycle timing
In this command, data of all addresses is erased. Data of all addresses becomes ”FFFFh”.
Actual ERASE starts at the fall of CS after the falll of the n-th clock from the start bit input.
In ERAL, status can be detected in the same manner as in WRITE command.
www.rohm.com
? 2011 ROHM Co., Ltd. All rights reserved.
13/40
2011.09 - Rev.G
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