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参数资料
| 型号： | BS616UV2019DCG85 |
| 厂商： | BRILLIANCE SEMICONDUCTOR, INC. |
| 英文描述： | Hex Buffer/Driver With Open-Drain Outputs 14-SOIC -40 to 85 |
| 中文描述： | 超低功率/电压CMOS SRAM的128K的× 16位 |
| 文件页数： | 4/8页 |
| 文件大小： | 255K |
| 代理商： | BS616UV2019DCG85 |
Revision 2.1
Jan.
2004
4
R0201-BS616LV1611
JEDEC
PARAMETER
NAME
PARAMETER
NAME
DESCRIPTION
UNIT
t
AVAX
t
RC
Read Cycle Time
70
--
55
--
ns
t
AVQV
t
AA
Address Access Time
--
70
--
55
ns
t
ELQV
t
ACS1
Chip Select Access Time
(CE1)
--
70
--
55
ns
t
ELQV
t
ACS2
Chip Select Access Time
(CE2)
--
70
--
55
ns
t
BA
t
BA
Data Byte Control Access Time
(LB,UB)
--
35
--
30
ns
t
GLQV
t
OE
Output Enable to Output Valid
--
35
--
30
ns
t
ELQX
t
CLZ
Chip Select to Output Low Z
(CE2,CE1)
10
--
10
--
ns
t
BE
t
BE
Data Byte Control to Output Low Z (LB,UB)
5
--
5
--
ns
t
GLQX
t
OLZ
Output Enable to Output in Low Z
5
--
5
--
ns
t
EHQZ
t
CHZ
Chip Deselect to Output in High Z (CE2,CE1)
--
35
--
30
ns
t
BDO
t
BDO
Data Byte Control to Output High Z (LB,UB)
--
35
--
30
ns
t
GHQZ
t
OHZ
Output Disable to Output in High Z
--
30
--
25
ns
t
AXOX
t
OH
Data Hold from Address Change
10
--
10
--
ns
AC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85oC )
READ CYCLE
AC TEST CONDITIONS
(Test Load and Input/Output Reference)
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
MUST BE
STEADY
MAY CHANGE
FROM H TO L
DON T CARE:
ANY CHANGE
PERMITTED
DOES NOT
APPLY
MUST BE
STEADY
WILL BE
CHANGE
FROM H TO L
CHANGE :
STATE
UNKNOWN
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
MAY CHANGE
FROM L TO H
WILL BE
CHANGE
FROM L TO H
,
BSI
BS616LV1611
(1)
1. tBA is 35ns/30ns (@speed=70ns/55ns) with address toggle .
tBA is 70ns/55ns (@speed=70ns/55ns) without address toggle .
NOTE :
Input Pulse Levels
Vcc / 0V
Input Rise and Fall Times
1V/ns
Input and Output
Timing Reference Level
0.5Vcc
Output Load
CL = 30pF+1TTL
CL = 100pF+1TTL
CYCLE TIME : 70ns
MIN. TYP. MAX.
Vcc = 2.7~5.5V
Vcc = 3.0~5.5V
CYCLE TIME : 55ns
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