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参数资料
| 型号： | BU-61580S3-110K |
| 厂商： | DATA DEVICE CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP70 |
| 封装： | 48.30 X 25.40 MM, 4.19 MM HEIGHT, DIP-70 |
| 文件页数： | 40/44页 |
| 文件大小： | 563K |
| 代理商： | BU-61580S3-110K |
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5
Data Device Corporation
www.ddc-web.com
BU-65170/61580/61585
H1 web-09/02-0
The J chip consists of a dual encoder/decoder, complete proto-
col for Bus Controller (BC), 1553A/B/McAir Remote Terminal
(RT), and Monitor (MT) modes; memory management and inter-
rupt logic; a flexible, buffered interface to a host processor bus
and optional external RAM; and 4K words of on-chip RAM.
Reference the region within the dotted line of FIGURE 1. Besides
realizing all the protocol, memory management, and interface
functions of the earlier AIM-HY'er series, the J chip includes a
large number of enhancements to facilitate hardware and soft-
ware design, and to further off-load the 1553 terminal's host
processor.
DECODERS
The default mode of operation for the BU-65170 RT and BU-
61580 BC/RT/MT requires a 16 MHz clock input. If needed, a
software programmable option allows the device to be operated
from a 12 MHz clock input. Most current 1553 decoders sample
using a 10 MHz or 12 MHz clock. In the 16 MHz mode (default
following a hardware or software reset), the ACE decoders sam-
ple 1553 serial data using the 16 MHz clock. In the 12 MHz
mode, the decoders sample using both clock edges; this pro-
vides a sampling rate of 24 MHz. The faster sampling rate for the
J chip’s Manchester II decoders provides superior performance
in terms of bit error rate and zero-crossing distortion tolerance.
For interfacing to fiber optic transceivers for MIL-STD-1773 appli-
cations, a transceiverless version of the J chip, the BU-65620,
can be used. These versions provide a pin-programmable option
for a direct interface to the single-ended outputs of a fiber optic
receiver. No external logic is needed.
TIME TAGGING
The ACE includes an internal read/writable Time Tag Register.
This register is a CPU read/writable 16-bit counter with a pro-
grammable resolution of either 2, 4, 8, 16, 32, or 64
s per LSB.
Also, the Time Tag Register may be clocked from an external
oscillator. Another option allows software-controlled increment-
ing of the Time Tag Register. This supports self-testing for the
Time Tag Register. For each message processed, the value of
the Time Tag register is loaded into the second location of the
respective descriptor stack entry (“TIME TAG WORD”) for both
BC and RT modes.
Additional provided options will: clear the Time Tag Register fol-
lowing a Synchronize (without data) mode command or load the
Time Tag Register following a Synchronize (with data) mode
command; enable an interrupt request and a bit setting in the
Interrupt Status Register when the Time Tag Register rolls over
from 0000 to FFFF. Assuming the Time Tag Register is not
loaded or reset, this will occur at approximately 4-second time
intervals, for 64
s/LSB resolution, down to 131 ms intervals, for
2
s/LSB resolution.
Another programmable option for RT mode is the automatic
clearing of the Service Request Status Word bit following the
ACE's response to a Transmit Vector Word mode command.
INTERRUPTS
The ACE series components provide many programmable
options for interrupt generation and handling. The interrupt out-
put pin (INT) has three software programmable modes of oper-
ation: a pulse, a level output cleared under software control, or a
level output automatically cleared following a read of the
Interrupt Status Register.
Individual interrupts are enabled by the Interrupt Mask Register.
The host processor may easily determine the cause of the inter-
rupt by using the Interrupt Status Register. The Interrupt Status
Register provides the current state of the interrupt conditions.
The Interrupt Status Register may be updated in two ways. In the
standard interrupt handling mode, a particular bit in the Interrupt
Status Register will be updated only if the condition exists and
the corresponding bit in the Interrupt Mask Register is enabled.
In the enhanced interrupt handling mode, a particular bit in the
Interrupt Status Register will be updated if the condition exists
regardless of the contents of the corresponding Interrupt Mask
Register bit. In any case, the respective Interrupt Mask Register
bit enables an interrupt for a particular condition.
ADDRESSING, INTERNAL REGISTERS, AND
MEMORY MANAGEMENT
The software interface of the BU-65170/61580 to the host
processor consists of 17 internal operational registers for normal
operation, an additional 8 test registers, plus 64K x 16 of shared
memory address space. The BU-65170/61580's 4K x 16 of inter-
nal RAM resides in this address space. Reference TABLE 2 and
24.
Definition of the address mapping and accessibility for the ACE's
17 non-test registers, and the test registers, is as follows:
Interrupt Mask Register is used to enable and disable interrupt
requests for various conditions.
Configuration Registers #1 and #2 are used to select the BU-
61580's mode of operation, and for software control of RT Status
Word bits, Active Memory Area, BC Stop-on-Error, RT Memory
Management mode selection, and control of the Time Tag oper-
ation.
Start/Reset Register is used for “command” type functions,
such as software reset, BC/MT Start, Interrupt Reset, Time Tag
Reset, and Time Tag Register Test. The Start/Reset Register
includes provisions for stopping the BC in its auto-repeat mode,
either at the end of the current message or at the end of the cur-
rent BC frame.
BC/RT Command Stack Pointer Register allows the host CPU
to determine the pointer location for the current or most recent
message when the BU-61580 is in BC or RT modes.
BC Control Word/RT Subaddress Control Word Register:In
BC mode, it allows host access to the current, or most recent BC
Control Word. The BC Control Word contains bits that select the
active bus and message format, enable off-line self-test, mask-
ing of Status Word bits, enable retries and interrupts, and spec-
ify MIL-STD-1553A or -1553B error handling. In RT mode, this
register allows host access to the current or most recent
Subaddress Control Word. The Subaddress Control Word is
used to select the memory management scheme and enable
interrupts for the current message. The read/write accessibility
can be used as an aid for testing the ACE.
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| BU-61580S3-442 | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP70 |
| BU-61580S3-480W | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP70 |
| BU-61580S3-820 | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP70 |
| BU-61580S6-420S | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP70 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| BU-61580S3-112 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:MIL-STD-1553/ARINC Bus Controller/RTU |
| BU-61580S3-122 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:MIL-STD-1553/ARINC Bus Controller/RTU |
| BU-61580S6-100 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:MIL-STD-1553/ARINC Bus Controller/RTU |
| BU-61580S6-110 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:MIL-STD-1553/ARINC Bus Controller/RTU |
| BU-61580S6-120 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:MIL-STD-1553/ARINC Bus Controller/RTU |
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