- 您现在的位置：买卖IC网 > PDF目录166578 > BU-61840B3-100S (DATA DEVICE CORP) 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, PBGA128 PDF资料下载
参数资料
| 型号： | BU-61840B3-100S |
| 厂商： | DATA DEVICE CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, PBGA128 |
| 封装： | 0.815 X 0.815 INCH, 0.140 INCH HEIGHT, BGA-128 |
| 文件页数： | 42/60页 |
| 文件大小： | 763K |
| 代理商： | BU-61840B3-100S |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页当前第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页
47
Data Device Corporation
www.ddc-web.com
BU-6174X/6184X/6186X
D-03/02-250
SELECT (I)
61
Generally connected to a CPU address decoder output to select the Enhanced Mini-
ACE for a transfer to/from either RAM or register.
B12
STRBD (I)
62
Strobe Data. Used in conjunction with SELECT to initiate and control the data transfer
cycle between the host processor and the ENHANCED MINI-ACE. STRBD must be
asserted low through the full duration of the transfer cycle.
B14
RD / WR
63
Read/Write. For a host processor access, RD/WR selects between reading and writing.
In the 16-bit buffered mode, if POL_SEL is logic "0, then RD/WR should be low (logic
“0") for read accesses and high (logic "1") for write accesses. If POL_SEL is logic "1",
or the interface is configured for a mode other than 16-bit buffered mode, then RD/WR
is high (logic "1") for read accesses and low (logic "0") for write accesses.
A12
ADDR_LAT(I) /
MEMOE (O)
14
Memory Output Enable or Address Latch.
In buffered mode, the ADDR_LAT input is used to configure the buffers for A15-A0,
SELECT, MEM/REG, and MSB/LSB (for 8-bit mode only) in latched mode (when low)
or transparent mode (when high). That is, the Enhanced Mini-ACE's internal transpar-
ent latches will track the values on A15-A0, SELECT, MEM/REG, and MSB/LSB when
ADDR_LAT is high, and latch the values when ADDR_LAT goes low.
In general, for interfacing to processors with a non-multiplexed address/data bus,
ADDR_LAT should be hardwired to logic "1". For interfacing to processors with a multi-
plexed address/data bus, ADDR_LAT should be connected to a signal that indicates a
valid address when ADDR_LAT is logic "1".
In transparent mode, MEMOE output signal is used to enable data outputs for external
RAM read cycles (normally connected to the OE input signal on external RAM chips).
V8
ZEROWAIT (I) /
MEMWR (O)
23
Memory Write or Zero Wait . In buffered mode, input signal (ZEROWAIT) used to select
between the zero wait mode (ZEROWAIT = “0") and the non-zero wait mode
(ZEROWAIT = "1").
In transparent mode, active low output signal (MEMWR) asserted low during memory
write transfers to strobe data into external RAM (normally connected to the WR input
signal on external RAM chips).
U8
16 / 8 (I) /
DTREQ (O)
24
Data Transfer Request or Data Bus Select. In buffered mode, input signal 16/8 used to
select between the 16 bit data transfer mode (16/8= "1") and the 8-bit data transfer
mode (16/8 = "0").
In transparent mode (16-bit only), active low level output signal DTREQ used to
request access to the processor/RAM interface bus (address and data buses).
V7
MSB / LSB (I) /
DTGRT (I)
64
Data Transfer Grant or Most Significant Byte/Least Significant Byte.
In 8-bit buffered mode, input signal (MSB/LSB) used to indicate which byte is currently
being transferred (MSB or LSB). The logic sense of MSB/LSB is controlled by the
POL_SEL input. MSB/LSB is not used in the 16-bit buffered mode.
In transparent mode, active low input signal (DTGRT) asserted in response to the
DTREQ output to indicate that control of the external processor/RAM bus has been
transferred from the host processor to the Enhanced Mini-ACE.
U6
TABLE 51. PROCESSOR INTERFACE CONTROL
SIGNAL NAME
DESCRIPTION
BU-6186XFX/GX
BU-6184XFX/GX
BU-6174XFX/GX
BALL
PIN
BU-61860BX
BU-61840BX
BU-61740BX
相关PDF资料 |
PDF描述 |
|---|---|
| BU-61840B3-202S | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, PBGA128 |
| BU-61840B3-302Y | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, PBGA128 |
| BU-61840B3-802W | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, PBGA128 |
| BU-61840B4-500L | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, PBGA128 |
| BU-61860B4-500Z | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, PBGA128 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| BU-61840B3NEW | 制造商:未知厂家 制造商全称:未知厂家 功能描述:MIL-STD-1553 Components |μ-ACE (Micro-ACE?) |
| BU-61843 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:MIL-STD-1553 Components |Enhanced Mini-ACE? |
| BU-61843F3-100 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Telecommunication IC |
| BU-61843F3-110 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Telecommunication IC |
| BU-61843F4-100 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Telecommunication IC |
发布紧急采购，3分钟左右您将得到回复。