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| 型号： | BU-61840B3-102W |
| 厂商： | DATA DEVICE CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, PBGA128 |
| 封装： | 0.815 X 0.815 INCH, 0.140 INCH HEIGHT, BGA-128 |
| 文件页数： | 22/60页 |
| 文件大小： | 763K |
| 代理商： | BU-61840B3-102W |
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29
Data Device Corporation
www.ddc-web.com
BU-6174X/6184X/6186X
D-03/02-250
RT COMMAND ILLEGALIZATION
The Enhanced Mini-ACE provides an internal mechanism for RT
Command Word illegalizing. By means of a 256-word area in
shared RAM, the host processor may designate that any mes-
sage be illegalized, based on the command word T/R bit, sub-
address, and word count/mode code fields. The Enhanced Mini-
ACE illegalization scheme provides the maximum in flexibility,
allowing any subset of the 4096 possible combinations of broad-
cast/own address, T/R bit, subaddress, and word count/mode
code to be illegalized.
The address map of the Enhanced Mini-ACE's illegalizing table
is illustrated in TABLE 41.
TABLE 41. ILLEGALIZATION TABLE MEMORY MAP
3FC
3BE
37D
3C2
381
33F
300
ADDRESS
Own Addr / Tx, SA 30. WC15-0
Own Addr / Rx, SA 31. MC15-0
Brdcst / Tx, SA 30. WC31-16
Own Addr / Tx, SA 1. WC15-0
Own Addr / Rx, SA 0. MC31-16
Brdcst / Rx, SA 31. MC31-16
Brdcst / Rx, SA 0. MC15-0
DESCRIPTION
3FD
3BF
37E
3C3
382
340
301
Own Addr / Tx, SA 30. WC31-16
Own Addr / Rx, SA 31. MC31-16
Brdcst / Tx, SA 31. MC15-0
Own Addr / Tx, SA 1. WC31-16
Own Addr / Rx, SA 1. WC15-0
Brdcst / Tx, SA 0. MC15-0
Brdcst / RX,SA 0. MC31-16
3FE
3C0
37F
383
341
302
Own Addr / Tx, SA 31. MC15-0
Own Addr / Tx, SA 0. MC15-0
Brdcst / Tx, SA 31. MC31-16
Own Addr / Rx, SA 1. WC31-16
Brdcst / Tx, SA 1.MC31-16
Brdcst / Rx, SA 1. WC15-0
3FF
3C1
380
342
303
Own Addr / Tx, SA 31. MC31-16
Own Addr / Tx, SA 0. MC31-16
Own Addr / Rx, SA 0. MC15-0
Brdcst / Tx, SA 1. WC15-0
Brdcst / Rx, SA 1. WC31-16
events/conditions include time tag rollover, RT address parity
error, RAM parity error, and BIT completed.
Bit 0 of the interrupt vector (interrupt status) word indicates
whether the entry is for a message interrupt event (if bit 0 is logic
"1") or a non-message interrupt event (if bit 0 is logic "0"). It is not
possible for one entry on the queue to indicate both a message
interrupt and a non-message interrupt.
As illustrated in FIGURE 10, for a message interrupt event, the
parameter word is a pointer. The pointer will reference the first
word of the RT or MT command stack descriptor (i.e., the Block
Status Word).
For a RAM Parity Error non-message interrupt, the parameter
will be the RAM address where the parity check failed. For the
RT address Parity Error, Protocol Self-test Complete, and Time
Tag rollover non-message interrupts, the parameter is not used;
it will have a value of 0000.
If enabled, an INTERRUPT STATUS QUEUE ROLLOVER inter-
rupt will be issued when the value of the queue pointer address
rolls over at a 64-word address boundary.
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| BU-61860B4-100K | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, PBGA128 |
| BU-61860B4-100 | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, PBGA128 |
| BU-61740B3-500Q | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, PBGA128 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| BU-61840B3NEW | 制造商:未知厂家 制造商全称:未知厂家 功能描述:MIL-STD-1553 Components |μ-ACE (Micro-ACE?) |
| BU-61843 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:MIL-STD-1553 Components |Enhanced Mini-ACE? |
| BU-61843F3-100 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Telecommunication IC |
| BU-61843F3-110 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Telecommunication IC |
| BU-61843F4-100 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Telecommunication IC |
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