参数资料
型号: BU-61843F3
厂商: DATA DEVICE CORP
元件分类: 微控制器/微处理器
英文描述: 2 CHANNEL(S), MIL-STD-1553 CONTROLLER, CQFP72
封装: 1 X 1 INCH, CERAMIC, FP-72
文件页数: 2/8页
文件大小: 89K
代理商: BU-61843F3
for other voltage(s), the use of a 5V transceiver entails the
use of a step-up, rather than step-down isolation
transformer. This increases the terminal's inherent input
impedance, reducing the demands on transformers and
system layout in meeting the MIL-STD-1553 impedance
requirement.
Improved Host Interface
Like the ACE and Mini-ACE series, the Enhanced Mini-ACE
supports a wide variety of processor interface configura-
tions. These include shared RAM and DMA configurations,
straightforward interfacing for 16-bit and 8-bit buses,
support
for
both
non-multiplexed
and
multiplexed
address/data buses, non-zero wait mode for interfacing to
processor address/data buses, and zero wait mode for
interfacing (for example) to microcontroller I/O ports. In
addition, the Enhanced Mini-ACE provides two major
improvements: (1) reduced maximum host access time for
shared RAM mode; and (2) increased DMA grant time for
the transparent/DMA mode.
Reduced maximum host access time
For the previous generation ACE and Mini-ACE terminals,
the maximum host holdoff time (time prior to the assertion
of the READYD* handshake signal) is 10 internal word transfer
cycles, resulting in an overall maximum holdoff time of
approximately 2.8
s, using a 16 MHz clock. With the Enhanced
Mini-ACE, this worst-case holdoff time is reduced significantly, to
a single internal transfer cycle. This results in a maximum
overall host transfer cycle time of approximately 500 ns at 16
MHz.
Increased DMA grant time
For the ACE and Mini-ACE in DMA mode, the maximum
request-to-grant time, which occurs prior to an RT start-of-
message sequence, is 4.0
s with a 16 MHz clock, or
3.5
s with a 12 MHz clock. For the Enhanced Mini-ACE
functioning as a MIL-STD-1553B RT, this time increases to
8.5
s at 10 MHz, 10 s at 16 MHz, 9 s at 12 MHz, and
10.5
s at 20 MHz. This provides greater flexibility, particu-
larly for systems in which a host has to arbitrate among
multiple DMA requestors.
2
TRANSCEIVER
A
CH. A
TRANSCEIVER
B
CH. B
DUAL
ENCODER/DECODER,
MULTIPROTOCOL
AND
MEMORY
MANAGEMENT
RT ADDRESS
AND
ADDRESS LATCH
4K X 16
OR
64K X 17
SHARED
RAM
ADDRESS BUS
PROCESSOR
AND
MEMORY
INTERFACE
LOGIC
DATA BUS
D15-D0
A15/CLK_SEL_1,
A14/CLK_SEL_0,
A13/Vcc,
A12/RTBOOT,
A11-A0
DATA
BUFFERS
ADDRESS
BUFFERS
PROCESSOR
DATA BUS
PROCESSOR
ADDRESS BUS
MISCELLANEOUS
CLK_IN,
MSTCLR,SSFLAG/EXT_TRG
RTAD4-RTAD0, RTADP
IOEN, READYD
ADDR_LAT/MEMOE, ZERO_WAIT/MEMWR,
8/16-BIT/DTREQ, POLARITY_SEL/DTACK
INT
TRANSPARENT/BUFFERED, STRBD, SELECT,
RD/WR, MEM/REG, TRIGGER_SEL/MEMENA-IN,
MSB/LSB/DTGRT
PROCESSOR
AND
MEMORY
CONTROL
INTERRUPT
REQUEST
TX/RX_A
TX/RX_B
TX_INH_A
TX_INH_B
RT-AD-LAT
INCMD/MCRST
+5V-RAM/UPADDREN
TRANSMITTER
INHIBITS
Figure 1. Block diagram
New Architectural Features: Bus Controller Mode
Multiprotocol Compliance
Like the ACE and Mini-ACE, the Enhanced Mini-ACE
provides full compliance to all of the commonly used data
bus standards, including MIL-STD-1553A, MIL-STD-1553B
Notice 2, STANAG 3838, General Dynamics 16PP303, and
McAirA3818, A5232, and A5690. For BC mode, the
appropriate protocol for individual RTs may be programmed
on a message-by-message basis.
Message sequence control
One of the major new architectural features of the Enhanced
Mini-ACE series is its advanced capability for BC message
sequence control. The Enhanced Mini-ACE supports highly
autonomous BC operation, which greatly offloads the band-
width of the host processor.
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