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参数资料
| 型号： | BU-65743F3-220 |
| 厂商： | DATA DEVICE CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP80 |
| 封装： | 0.880 INCH, CERAMIC, QFP-80 |
| 文件页数： | 3/75页 |
| 文件大小： | 532K |
| 代理商： | BU-65743F3-220 |
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11
Data Device Corporation
www.ddc-web.com
BU-65743/65843/65863/65864
D-06/04-0
PCI_INTERRUPT ACTIVE: When set to '1', indicates that PCI
Mini-ACE Mark3/Micro-ACE TE has asserted it's interrupt pin.
The three possible sources (if enabled and active) are the ACE
core, FailSafe timer and BAR1 DRR_DATA_DISCARD.
FIFO NOT EMPTY: When set to '1', indicates that the write FIFO
is not empty.
BAR1 DRR_DATA_DISCARD: If the data discard timer times out
while waiting for a retry on a BAR1 access, this bit will be set. If
BAR1 read is discarded, it may have caused an action (for
example clearing an ACE interrupt) that has not been recognized
by the PCI MASTER.
FAIL SAFE ERROR: If not in FAIL_SAFE OFF mode and fail safe
error occurs (ACE does not respond), this bit will be set. Failsafe
errors are extremely unlikely.
DRR_HOLD: When '0', a delayed read request is discarded if the
PCI Mini-ACE Mark3/Micro-ACE TE has obtained requested
data and a different transaction is requested. When '1', delayed
read request is held until master repeats original request or time-
out occurs.
DRR_HOLD
31 (MSB)
DESCRIPTION
BIT
TABLE 10. REG1 FAIL-SAFE OPERATION/INTERRUPT REGISTER
(READ/WRITE 804H)
RESERVED, WRITE AS 0
30
BAR1 DRR_DATA_DISCARD INTERRUPT ENABLE
20
RESERVED, WRITE AS 0
22
PCI MINI-ACE MARK3/MICRO-ACE TE INTERRUPT ENABLE
21
FAILSAFE INTERRUPT ENABLE
19
FAILSAFE INTERRUPT AUTOCLEAR ENABLE
18
FAILSAFE MODE - BIT 1 (MSB)
17
FAILSAFE MODE - BIT 0 (LSB)
16
RESERVED , WRITE AS 0
15
RESERVED, WRITE AS 0
0(LSB)
This register will be all 0s after RST#, except for bit 17 will be 1 (Fail-safe mode =
fail-safe halt). Note that Failsafe errors are extremely unlikely.
BITS 30 - 22: Reserved, write as 0s
PCI MINI-ACE MARK3/MICRO-ACE TE INTERRUPT ENABLE:
Must be set to "1".
BAR1 DRR_DATA_DISCARD INTERRUPT ENABLE: Enables
interrupt to occur on a BAR1 delayed read timeout.
FAILSAFE INTERRUPT ENABLE: When set to a "1", an interrupt
is generated if not in FAILSAFE OFF mode and a FAILSAFE
error is detected.
FAILSAFE INTERRUPT AUTOCLEAR ENABLE: If set, causes
interrupt and the FAIL_SAFE ERROR bit (REG0-bit 22) to be
cleared whenever upper word of REG0 is read by the PCI MAS-
TER. If not set, bit 1 in Reg 7 must be used to clear Failsafe inter-
rupts.
FAILSAFE MODE: Fail Safe Errors occur when the internal ACE
fails to assert it's hand-shake signal within 1 millisecond (pro-
grammable) of when the internal Strobe or Request signal is
asserted. Four possible FAILSAFE Modes determine how this
situation is handled.
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