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| 型号： | BU-65743F3-320 |
| 厂商： | DATA DEVICE CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP80 |
| 封装： | 0.880 INCH, CERAMIC, QFP-80 |
| 文件页数： | 50/75页 |
| 文件大小： | 532K |
| 代理商： | BU-65743F3-320 |
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54
Data Device Corporation
www.ddc-web.com
BU-65743/65843/65863/65864
D-06/04-0
SSFLAG
(I)/EXT_TRIG (I)
20
U10
Subsystem Flag (RT) or External Trigger (BC/Word Monitor) input. In RT mode with standard status word,
if this input is asserted low, the Subsystem Flag bit will be set in the PCI MINI-ACE MARK3/MICRO-ACE
TE's RT Status Word. If the SSFLAG input is logic "0" while bit 8 of Configuration Register #1 has been
programmed to logic "1" (cleared), the Subsystem Flag RT Status Word bit will become logic "1", but bit
8 of Configuration Register #1, SUBSYSTEM FLAG, will return logic "1" when read. That is, the sense
on the SSFLAG input has no effect on the SUBSYSTEM FLAG register bit. This input has no meaning in
RT mode with alternate status word.
In the non-enhanced BC mode, this signal operates as an External Trigger input. In BC mode, if the exter-
nal BC Start option is enabled (bit 7 of Configuration Register #1), a low to high transition on this input
will issue a BC Start command, starting execution of the current BC frame.
In the enhanced BC mode, during the execution of a Wait for External Trigger (WTG) instruction, the PCI
Mini-ACE Mark3/Micro-ACE TE BC will wait for a low-to-high transition on EXT_TRIG before proceeding
to the next instruction.
In the Word Monitor mode, if the external trigger is enabled (bit 7 of Configuration Register #1), a low to
high transition on this input will initiate a monitor start. (RT the monitor on low). In all modes this input
operates as an external trigger, this signal should remain asserted for at least 4 1533_CLK ticks after it
goes high. This input has no effect in Message Monitor mode.
TABLE 72. PROCESSOR INTERFACE CONTROL
SIGNAL NAME
DESCRIPTION
BALL
PIN
L9
BALL
5V
3V
RTAD4 (MSB) (I)
80
RT Address inputs (5V tolerant). If bit 5 of Configuration Register #6, RT ADDRESS SOURCE, is pro-
grammed to logic "0" (default), then the PCI Mini-ACE Mark3/Micro-ACE TE's RT address is provided by
means of these 5 input signals. In addition, if RT ADDRESS SOURCE is logic "0", the source of RT
address parity is RTADP.
There are many methods for using these input signals for designating the PCI Mini-ACE Mark3/Micro-
ACE TE's RT address. For details, refer to the description of RT_AD_LAT.
If RT ADDRESS SOURCE is programmed to logic "1", then the PCI Mini-ACE Mark3/Micro-ACE TE's
source for its RT address and parity is under software control, when the SW writes to config reg #5 inter-
nal address bits 4-0 will be latched from PCI data bus bit AD5-1 and internal RTADP will be latched from
PCI data bus bit AD0. In this case, the RTAD4-RTAD0 and RTADP signals are not used.
RTAD3 (I)
7
RTAD2 (I)
2
RTAD1 (I)
1
RTAD0 (LSB) (I)
6
TABLE 73. RT ADDRESS
A4
D10
C15
E6
A6
A10
C9
A8
B9
C11
Remote Terminal Address Parity. This input signal (5V tolerant) must provide an odd parity sum with
RTAD4-RTAD0 in order for the RT to respond to non-broadcast commands. That is, there must be an
odd number of logic "1"s from among RTAD-4-RTAD0 and RTADP
RTADP (I)
13
E9
D6
RT Address Latch.
Input signal (5V tolerant) used to control the PCI Mini-ACE Mark3/Micro-ACE TE's
internal RT address latch. If RT_AD_LAT is connected to logic "0", then the PCI Mini-ACE Mark3/Micro-
ACE TE RT is configured to accept a hardwired (transparent) RT address from RTAD4-RTAD0 and RTADP.
If RT_AD_LAT is initially logic "0", and then transitions to logic "1", the values presented on RTAD4-RTAD0
and RTADP will be latched internally on the rising edge of RT_AD_LAT.
If RT_AD_LAT is connected to logic "1", then the PCI Mini-ACE Mark3/Micro-ACE TE's RT address is
latchable under host processor control. In this case, there are two possibilities: (1) If bit 5 of Configuration
Register #6, RT ADDRESS SOURCE, is programmed to logic "0" (default), then the source of the RT
Address is the RTAD4-RTAD0 and RTADP input signals; (2) If RT ADDRESS SOURCE is programmed to
logic "1", then the source of the RT Address is the lower 6 bits of the PCI data bus, D5-D1 (for RTAD4-0)
and D0 (for RTADP).
In either of these two cases (with RT_AD_LAT = "1"), the processor will cause the RT address to be latched
by: (1) writing bit 15 of Configuration Register #3, ENHANCED MODE, to logic "1"; (2) writing bit 3 of
Configuration Register #4, LATCH RT ADDRESS WITH CONFIGURATION REGISTER #5, to logic "1"; and
(3) writing to Configuration Register #5. In the case of RT ADDRESS SOURCE = "1", then the values of RT
address and RT address parity must be written to the lower 6 bits of Configuration Register #5, via D5-D0.
In the case where RT ADDRESS SOURCE = "0", the bit values presented on D5-D0 become "don't care".
RT_AD_LAT (I)
12
D9
C7
SIGNAL NAME
DESCRIPTION
BALL
PIN
BALL
5V
3V
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