参数资料
| 型号： | BU2152FS-E2 |
| 厂商： | Rohm Semiconductor |
| 文件页数： | 16/18页 |
| 文件大小： | 0K |
| 描述： | IC DRVR SER/PAR I/O 24B SSOPA32 |
| 标准包装： | 1 |
| 类型： | 驱动器 |
| 电源电压： | 2.7 V ~ 5.5 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-SSOP |
| 供应商设备封装： | 32-SSOPA |
| 包装： | 标准包装 |
| 其它名称： | BU2152FS-E2DKR |
BU2050F,BU2092F,BU2092FV,BU2099FV,BD7851FP,BU2152FS
Technical Note
7/24
www.rohm.com
2009.06 - Rev.A
2009 ROHM Co., Ltd. All rights reserved.
【BU2050F】
●Pin descriptions
Pin No.
Pin Name
Function
1
P3
Parallel Data Output
2
P4
3
P5
4
VSS
GND
5
P6
Parallel Data Output
6
P7
7
P8
8
DATA
Serial Data Input
9
CLK
Clock Signal Input
10
STB
Strobe Signal Input
In case of “L”, the data of shift register outputs.
In case of “H”, all parallel outputs and data of latch circuit do not change.
11
CLR
Reset Signal Input
In case of “L”, the data of latch circuit reset, and all parallel output (P1～P8) can be L.
Normally CLR=H
12
P1
Parallel Data output
13
P2
14
VDD
Power Supply
●Timing chart
Fig. 2
1. After the power is turned on and the voltage is stabilized, STB should be activated, after clocking 8 data bits into the
DATA pin.
2. Pn parallel output data of the shift register is set after the 8
th clock by the STB.
3. Since the STB is level latch, data is retained in the “L” section and renewed in the “H” section of the STB.
［Function explanation］
·
A latch circuit has the reset function, which is common in all bits. In case of CLR terminal is “L”, the latch
circuit is reset non-synchronously without the other input condition, and all parallel output can be “L”.
·
A serial data inputted from DATA terminal is read in shift register with synchronized rising of clock.
In case of STB is “L” (CLR is ”H”), transmit the data which read in the shift register to latch circuit, and
outputs from the parallel data output terminal (P1～P8).
In case of STB is “H”, all parallel outputs and the data of latch do not change.
CLK
STB
DATA
DATA8
DATA7
DATA6
DATA2
DATA1
Pn
Previous DATA
DATA
CLR
“L”
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相关代理商/技术参数 |
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