参数资料
| 型号： | BU4SU69G2-TR |
| 厂商： | Rohm Semiconductor |
| 文件页数： | 2/14页 |
| 文件大小： | 0K |
| 描述： | IC INVERTER SCHMITT SGL SSOP5 |
| 标准包装： | 1 |
| 系列： | 4S |
| 逻辑类型： | 反相器 |
| 电路数： | 1 |
| 输入数： | 1 |
| 电源电压： | 3 V ~ 16 V |
| 电流 - 静态（最大值）： | 1µA |
| 输出电流高，低： | 3.4mA，3.4mA |
| 逻辑电平 - 低： | 1 V ~ 2.5 V |
| 逻辑电平 - 高： | 4 V ~ 12.5 V |
| 额定电压和最大 CL 时的最大传播延迟： | 25ns @ 15V，50pF |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 供应商设备封装： | 5-SSOP |
| 封装/外壳： | 6-TFSOP（0.063"，1.60mm 宽），5 引线 |
| 包装： | 标准包装 |
| 其它名称： | BU4SU69G2-DKR BU4SU69G2-DKR-ND BU4SU69G2DKR |
10
Commercial Temperature Range
IDT72V8981 3.3V Time Slot Interchange
Digital Switch 128 x 128
CS
DS
5702 drw1
5
R/
W
A5-A0
D7-D0
DTA
tCSS
tRWS
tADS
tAKD
tRDS
tSWD
tFWS
tCSH
tRWH
tADH
tAKH
tRDZ
tDHT
Figure 10. Processor Bus
Symbol
Characteristics
Min.
Typ.(2)
Max.
Unit
Test Conditions
tCSS
Chip Select Setup Time
0
ns
tRWS
Read/WriteSetupTime
5
ns
tADS
Address Setup Time
5
ns
tAKD
Acknowledgment Delay Fast
40
60
ns
C
L = 150pF
tAKD
Acknowledgment Delay Slow
4.5
cycles
C4i cycles(4)
tFWS
Fast Write Data Setup Time
10
20
ns
tSWD
Slow Write Data Delay
2.0
1.7
cycles
C4i cycles
tRDS
Read Data Setup Time
0.5
cycles
C4i cycles, C
L = 150pF
tDHT
Data Hold Time Read
20
50
75
ns
R
L = 1K
(3), C
L = 150pF
tDHT
Data Hold Time Write
10
ns
tRDZ
Read Data to High Impedance
10
50
ns
R
L = 1K
(3), C
L = 150pF
tCSH
Chip Select Hold Time
0
5
ns
tRWH
Read/Write Hold Time
0
5
ns
tADH
Address Hold Time
0
5
ns
tAKH
Acknowledgment Hold Time
20
40
ns
R
L = 1K
(3), C
L = 150pF
NOTE:
1. Timing is over recommended temperature and power supply voltages.
2. Typical figures are at 25
°C and are for design aid only; not guaranteed and not subject to production testing.
3. High Impedance is measured by pulling to the appropriate rail with R
L, with timing corrected to cancel time taken to discharge CL.
4. Processor accesses are dependent on the
C4i clock, and so some things are expressed as multiples of the C4i.
AC ELECTRICAL CHARACTERISTICS (1)
PROCESSOR BUS
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