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| 型号： | BUF20820AIDCPRE4 |
| 厂商： | Texas Instruments |
| 文件页数： | 2/29页 |
| 文件大小： | 0K |
| 描述： | IC 18CH PROG V-REF GEN 38-HTSSOP |
| 标准包装： | 2,000 |
| 应用： | TFT-LCD 面板：伽玛缓冲器，VCOM 驱动器 |
| 输出类型： | 满摆幅 |
| 电路数： | 18 |
| 电流 - 电源： | 18mA |
| 电流 - 输出 / 通道： | 100mA |
| 电压 - 电源，单路/双路(±)： | 7 V ~ 18 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 38-TFSOP （0.173"，4.40mm 宽）裸露焊盘 |
| 供应商设备封装： | 38-HTSSOP |
| 包装： | 带卷 (TR) |
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BUF20820
SBOS330E DECEMBER 2005 REVISED OCTOBER 2008
www.ti.com
10
addressed register, the master continues to send data for
the next register. The BUF20820 automatically and
sequentially steps through subsequent registers as
additional data is sent. The process continues until all
desired registers have been updated or a STOP condition
is sent.
To write to multiple DAC registers:
1.
Send a START condition on the bus.
2.
Send the device address and read/write bit = LOW.
The BUF20820 will acknowledge this byte.
3.
Send either the DAC_1 address byte to start at the first
DAC, or send the address byte for whichever DAC will
be the first in the sequence of DACs to be updated.
The BUF20820 will begin with this DAC and step
through subsequent DACs in sequential order.
4.
Send the bytes of data; begin by sending the most
significant byte (bits D15D8, of which only bits D9
and D8 have meaning, and bits D15D14 must not be
01), followed by the least significant byte (bits D7D0).
The first two bytes are for the DAC addressed in step
3 above. Its register is automatically updated after
receiving the second byte. The next two bytes are for
the following DAC. That DAC register is updated after
receiving the fourth byte. This process continues until
the registers of all following DACs have been updated.
The last address, 10100, is the address of the write
disable bit and cannot be accessed using this method.
It must be written using the write to a single DAC
register procedure.
5.
Send a STOP condition on the bus.
The BUF20820 will acknowledge each byte. To terminate
communication, send a STOP or START condition on the
bus. Only DAC registers that have received both bytes of
data will be updated.
Reading:
Reading a DAC register will return the data stored in the
DAC. This data can differ from the data stored in the DAC
register. See the Output Latch section.
To read the DAC value:
1.
Send a START condition on the bus.
2.
Send the device address and read/write bit = LOW.
The BUF20820 will acknowledge this byte.
3.
Send the DAC address byte. Bits D7D5 must be set
to 0; Bits D4D0 are the DAC address. Only DAC
addresses 00000 to 10100 are valid and will be
acknowledged. For address 10100, only D0 has
meaning. This bit is the write disable bit.
4.
Send a START or STOP/START condition on the bus.
5.
Send
correct
device
address
and
read/write
bit = HIGH. The BUF20820 will acknowledge this
byte.
6.
Receive two bytes of data. They are for the specified
DAC. The first received byte is the most significant
byte (bits D15D8, only bits D9 and D8 have
meaning); the next byte is the least significant byte
(bits D7D0).
7.
Acknowledge after receiving the first byte.
8.
Do not acknowledge the second byte to end the read
transaction.
Communication may be terminated by sending a
premature STOP or START condition on the bus, or by not
sending the acknowledge.
To Read Multiple DACs:
1.
Send a START condition on the bus.
2.
Send the device address and read/write bit = LOW.
The BUF20820 will acknowledge this byte.
3.
Send either the DAC_1 address byte to start at the first
DAC, or send the address byte for whichever DAC will
be the first in the sequence of DACs to be read. The
BUF20820 will begin with this DAC and step through
subsequent DACs in sequential order.
4.
Send a START or STOP/START condition on the bus.
5.
Send
correct
device
address
and
read/write
bit = HIGH. The BUF20820 will acknowledge this
byte.
6.
Receive two bytes of data. They are for the specified
DAC. The first received byte is the most significant
byte (bits D15D8, only bits D9 and D8 have
meaning), the next byte is the least significant byte
(bits D7D0).
7.
Acknowledge after receiving each byte of data except
for the last byte. The acknowledge bit of the last byte
should be HIGH to end the read operation.
8.
When all desired DACs have been read, send a STOP
or START condition on the bus.
Communication may be terminated by sending a
premature STOP or START condition on the bus, or by not
sending the acknowledge.
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