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参数资料
| 型号： | BX80525U500512E |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 500 MHz, MICROPROCESSOR, XMA |
| 文件页数： | 8/94页 |
| 文件大小： | 898K |
| 代理商： | BX80525U500512E |
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Pentium
III Processor at 450 MHz, 500 MHz, 533B MHz, 550 MHz, 600/600B MHz
16
Datasheet
2.4.1
Processor VCCCORE Decoupling
Regulator solutions need to provide bulk capacitance with a low Effective Series Resistance (ESR)
and keep an interconnect resistance from the regulator (or VRM pins) to the SC242 connector of
less than 0.3 m
. This can be accomplished by keeping a maximum distance of 1.0 inches between
the regulator output and SC242 connector. The recommended VCC
CORE interconnect is a 2.0 inch
wide by 1.0 inch long (maximum distance between the SC242 connector and the VRM connector)
plane segment with a 1-ounce plating. Bulk decoupling for the large current swings when the part
is powering on, or entering/exiting low power states, is provided on the voltage regulation module
(VRM). If using Intel’s enabled VRM solutions see developer.intel.com for the specification and a
list of qualified vendors. The VCC
CORE input should be capable of delivering a recommended
minimum dICC
CORE/dt (defined in Table 7) while maintaining the required tolerances (also defined in
Table 7).
2.4.2
Processor System Bus AGTL+ Decoupling
The Pentium III processor contains high frequency decoupling capacitance on the processor
substrate; bulk decoupling must be provided for by the system baseboard for proper AGTL+ bus
operation. See AP-906, 100 MHz AGTL+ Layout Guidelines for the Pentium III Processor and
Intel 440BX AGPset (Order Number 245086) or the appropriat platform design guide, AP-907,
Pentium III Processor Power Distribution Guidelines (Order Number 245085), and the GTL+
buffer specification in the Pentium II Processor Developer's Manual (Order Number 243502) for
more information.
2.5
Processor System Bus Clock and Processor Clocking
The BCLK input directly controls the operating speed of the Pentium III processor system bus
interface. All Pentium III processor system bus timing parameters are specified with respect to the
rising edge of the BCLK input. See the P6 Family of Processors Hardware Developer's Manual
(Order Number 244001) for further details.
2.5.1
Mixing Processors of Different Frequencies
In 2-way MP systems, mixing processors of different internal core or system bus frequencies is not
supported and has not been validated by Intel. Pentium III processors do not support a variable
multiplier ratio; therefore, adjusting the ratio setting to a common clock frequency is not valid.
However, mixing processors of the same frequency but of different steppings is supported.
2.6
Voltage Identification
There are five voltage identification pins on the SC242 connector. These pins can be used to
support automatic selection of power supply voltages. These pins are not signals, but are either an
open circuit or a short circuit to V
SS on the processor. The combination of opens and shorts defines
the voltage required by the processor core. The VID pins are needed to cleanly support voltage
specification variations on current and future Pentium III processors. VID[4:0] are defined in Table
3. A ‘1’ in this table refers to an open pin and a ‘0’ refers to a short to ground. The power supply
must supply the voltage that is requested or disable itself.
相关PDF资料 |
PDF描述 |
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| BX80525U533512E | 32-BIT, 533 MHz, MICROPROCESSOR, XMA |
| BX80525U550512E | 32-BIT, 550 MHz, MICROPROCESSOR, XMA |
| BX80525U450512E | 32-BIT, 450 MHz, MICROPROCESSOR, XMA |
| BX80526F500256E | 32-BIT, 500 MHz, MICROPROCESSOR, PPGA370 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| BX80525U533256EB | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Microprocessor |
| BX80525U550256E | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Microprocessor |
| BX80525U600256E | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Microprocessor |
| BX80525U600256EB | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Microprocessor |
| BX80525U650256 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Microprocessor |
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