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参数资料
| 型号： | BX80526C866256E |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 866 MHz, MICROPROCESSOR, PPGA370 |
| 封装： | FCPGA2-370 |
| 文件页数： | 16/94页 |
| 文件大小： | 1014K |
| 代理商： | BX80526C866256E |
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Datasheet
23
Pentium III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
The groups and the signals contained within each group are shown in Table 3 and Table 4. Refer to
Section 7.0 foradescription ofthese signals.
NOTES:
1. See Section 7.0 for information on the these signals.
2. The BR0# pin is the only BREQ# signal that is bidirectional. See Section 7.0 for more information. The
internal BREQ# signals are mapped onto the BR[1:0]# pins after the agent ID is determined.
3. These signals are specified for VccCMOS (1.5 V for the Pentium III processor) operation.
4. These signals are 2.5 V tolerant.
5. VCCCORE is the power supply for the processor core and is described in Section 2.6.
VID[3:0] is described in Section 2.6.
VTT is used to terminate the system bus and generate VREF on the motherboard.
VSS is system ground.
VCC1.5, VCC2.5, VccCMOS are described in Section 2.3.
BSEL[1:0] is described in Section 2.8.2 and Section 7.0.
All other signals are described in Section 7.0.
6. RESET# must always be terminated to VTT on the motherboard, on-die termination is not provided for this
signal.
7. This signal is not supported by all processors. Refer to the Pentium III Processor Specification Update for a
complete listing of processors that support this pin.
8. This signal is used to control the value of the processor on-die termination resistance. Refer to the platform
design guide for the recommended pull-down resistor value.
Table 3.
System Bus Signal Groups 1
Group Name
Signals
AGTL+ Input
BPRI#, BR1#7, DEFER#, RESET# 6,RESET2#, RS[2:0]#, RSP#, TRDY#
AGTL+ Output
PRDY#
AGTL+ I/O
A[35:3]#, ADS#, AERR#, AP[1:0]#, BERR#, BINIT#, BNR#, BP[3:2]#, BPM[1:0]#,
BR0#2, D[63:0]#, DBSY#, DEP[7:0]#, DRDY#, HIT#, HITM#, LOCK#, REQ[4:0]#, RP#
CMOS Input3
A20M#, FLUSH#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PREQ#, SLP#, SMI#,
STPCLK#
CMOS Input4
PWRGOOD
CMOS Output3
FERR#, IERR#, THERMTRIP#
System Bus
Clock4
BCLK
APIC Clock4
PICCLK
APIC I/O3
PICD[1:0]
Power/Other5
BSEL[1:0], CLKREF, CPUPRES#, EDGCTRL, PLL[2:1], RESET2#, SLEWCTRL,
THERMDN, THERMDP, RTTCTRL8,VCOREDET, VID[3:0], VCC1.5, VCC2.5, VCCCMOS,
VCCCORE,VREF,VSS,VTT, Reserved
Table 4.
System Bus Signal Groups (AGTL)1 (Sheet 1 of 2)
Group Name
Signals
AGTL Input9
BPRI#, BR1#7, DEFER#, RESET#6, RSP#, TRDY#, RS[2:0]#
AGTL Output9
PRDY#
AGTL I/O9
A[35:3]#, ADS#, AERR#, AP[1:0]#, BERR#, BINIT#, BNR#, BP[3:2]#, BPM[1:0]#,
BR0#2, D[63:0]#, DBSY#, DEP[7:0]#, DRDY#, HIT#, HITM#, LOCK#, REQ[4:0]#, RP#,
CMOS Input3
A20M#, FLUSH#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PREQ#, SLP#, SMI#,
STPCLK#
CMOS Input
(1.8 V)
PWRGOOD
CMOS Output
FERR#3, IERR#3, THERMTRIP#3, VID[3:0]13, BSEL[1:0]13
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