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参数资料
| 型号： | BX80526C866256E |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 866 MHz, MICROPROCESSOR, PPGA370 |
| 封装： | FCPGA2-370 |
| 文件页数： | 9/94页 |
| 文件大小： | 1014K |
| 代理商： | BX80526C866256E |
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Datasheet
17
Pentium III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
While in the Sleep state, the processor is capable of entering its lowest power state, the Deep Sleep
state, by stopping the BCLK input (see Section 2.2.6). Once in the Sleep or Deep Sleep states, the
SLP# pin can be deasserted if another asynchronous system bus event occurs. The SLP# pin has a
minimum assertion of one BCLK period.
2.2.6
Deep Sleep State—State 6
The Deep Sleep state is the lowest power state the processor can enter while maintaining context.
The Deep Sleep state is entered by stopping the BCLK1 input (after the Sleep state was entered
from the assertion of the SLP# pin). The processor is in Deep Sleep state immediately after BCLK
is stopped. It is recommended that the BCLK
1 input be held low during the Deep Sleep State.
Stopping of the BCLK1 input lowers the overall current consumption to leakage levels.
To re-enter the Sleep state, the BCLK input must be restarted. A period of 1 ms (to allow for PLL
stabilization) must occur before the processor can be considered to be in the Sleep state. Once in
the Sleep state, the SLP# pin can be deasserted to re-enter the Stop-Grant state.
While in Deep Sleep state, the processor is incapable of responding to snoop transactions or
latching interrupt signals. No transitions or assertions of signals are allowed on the system bus
while the processor is in Deep Sleep state. Any transition on an input signal before the processor
has returned to Stop-Grant state will result in unpredictable behavior.
2.2.7
Clock Control
BCLK
2 provides the clock signal for the processor and on die L2 cache. During AutoHALT Power
Down and Stop-Grant states, the processor will process a system bus snoop. The processor does not
stop the clock to the L2 cache during AutoHALT Power Down or Stop-Grant states. Entrance into
the Halt/Grant Snoop state allows the L2 cache to be snooped, similar to the Normal state.
When the processor is in Sleep and Deep Sleep states, it does not respond to interrupts or snoop
transactions. During the Sleep state, the internal clock to the L2 cache is not stopped. During the
Deep Sleep state, the internal clock to the L2 cache is stopped. The internal clock to the L2 cache is
restarted only after the internal clocking mechanism for the processor is stable (i.e., the processor
has re-entered Sleep state).
PICCLK should not be removed during the AutoHALT Power Down or Stop-Grant states.
PICCLK can be removed during the Sleep or Deep Sleep states. When transitioning from the Deep
Sleep state to the Sleep state, PICCLK must be restarted with BCLK.
2
2.3
Power and Ground Pins
The operating voltage of the Pentium III processor for the PGA370 socket is the same for the core
and the L2 cache; VCCCORE. There are four pins defined on the package for voltage identification
(VID). These pins specify the voltage required by the processor core. These have been added to
cleanly support voltage specification variations on current and future processors.
For clean on-chip power and voltage reference distribution, the Pentium III processors in the
PGA370 socket have 75 VCCCORE,8VREF (7 for AGTL platforms), 15 VTT, and 77 VSS (ground)
inputs. VCCCORE inputs supply the processor core, including the on-die L2 cache. VTT inputs
1. For processors using AGTL level bus with differential clocking, the deep sleep state is entered by stopping BCLK and BCLK# input.
2. For processors using AGTL level bus with differential clocking this would also include the BCLK# signal as well.
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相关代理商/技术参数 |
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|---|---|
| BX80526F1000128 | 制造商:Intel 功能描述:32-BIT, 1000 MHz, MICROPROCESSOR, CPGA370 |
| BX80526H800256E827304 | 制造商:Intel 功能描述:MPU PENTIUM III CISC 64BIT 0.18UM 800MHZ 370PIN FCPGA - Boxed Product (Development Kits) |
| BX80526KY7002M | 制造商:Intel 功能描述:MPU PENTIUM III XEON 64-BIT 0.18UM 700MHZ - Boxed Product (Development Kits) |
| BX80526KY9002M | 制造商:Intel 功能描述:MPU PENTIUM III XEON 64-BIT 0.18UM 900MHZ - Boxed Product (Development Kits) |
| BX80528JK150GR | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Microprocessor |
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