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参数资料
| 型号： | BX80526F650256E |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 650 MHz, MICROPROCESSOR, PPGA370 |
| 封装： | FCPGA2-370 |
| 文件页数： | 5/94页 |
| 文件大小： | 1014K |
| 代理商： | BX80526F650256E |
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Datasheet
13
Pentium III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
2.0
Electrical Specifications
2.1
Processor System Bus and VREF
The Pentium III processor signals use a variation of the low voltage Gunning Transceiver Logic
(GTL) signaling technology.
The Pentium Pro processor system bus specification is similar to the GTL specification, but was
enhanced to provide larger noise margins and reduced ringing. The improvements are
accomplished by increasing the termination voltage level and controlling the edge rates. This
specification is different from the GTL specification, and is referred to as GTL+. For more
information on GTL+ specifications, see the GTL+ buffer specification in the Intel
Pentium II
Processor Developer’s Manual.
Current P6 family processors vary from the Pentium Pro processor in their output buffer
implementation. The buffers that drive the system bus signals on the Celeron, Pentium II, and
Pentium III processors are actively driven to VTT for one clock cycle after the low to high transition
to improve rise times. These signals should still be considered open-drain and require termination
to a supply that provides the high signal level. Because this specification is different from the
standard GTL+ specification, it is referred to as AGTL+, or Assisted GTL+ in this and other
documentation. AGTL+ logic and GTL+ logic are compatible with each other and may both be
used on the same system bus. For more information on AGTL+ routing, see the appropriate
platform design guide.
Note that some Pentium III processors with CPUID 068xh support the AGTL specification in
addition to the AGTL+ specification. AGTL logic and AGTL+ logic are not compatible with each
other due to differences with the signal switching levels. Processors that do not support the AGTL
specification cannot be installed into platforms where the chipset only supports the AGTL signal
levels. For more information on AGTL or AGTL+ routing, please refer to the appropriate platform
design guide.
Both AGTL and AGTL+ inputs use differential receivers which require a reference signal (VREF).
VREF is used by the receivers to determine if a signal is a logical 0 or a logical 1, and is supplied by
the motherboard to the PGA370 socket for the processor core. Local VREF copies should also be
generated on the motherboard for all other devices on the AGTL+ (AGTL) system bus. Termination
(usually a resistor at each end of the signal trace) is used to pull the bus up to the high voltage level
and to control reflections on the transmission line. The processor contains on-die termination
resistors that provide termination for one end of the bus, except for RESET#. These specifications
assume another resistor at the end of each signal trace to ensure adequate signal quality for the
AGTL+ (AGTL) signals and provide backwards compatibility for the Celeron processor; see Table
12 for the bus termination voltage specifications for AGTL+. Refer to the Intel Pentium II
Processor Developer’s Manual for the AGTL+ bus specification. Solutions exist for single-ended
termination as well, though this implementation changes system design and eliminate backwards
compatibility for Celeron processors in the PPGA package. Single-ended termination designs must
still provide an AGTL+ (AGTL) termination resistor on the motherboard for the RESET# signal.
Figure 2 is a schematic representation of the AGTL+ (AGTL) bus topology for the Pentium III
processors in the PGA370 socket. Figure 3 is a schematic representation of the AGTL+/AGTL bus
topology in a dual-processor configuration with Pentium III processors in the PGA370 socket.
Both AGTL+ and AGTL bus depend on incident wave switching. Therefore, timing calculations for
AGTL+ or AGTL signals are based on flight time as opposed to capacitive deratings. Analog signal
simulation of the system bus including trace lengths is highly recommended when designing a
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