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参数资料
| 型号： | BX80526F733256E |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 733 MHz, MICROPROCESSOR, PPGA370 |
| 封装： | FCPGA2-370 |
| 文件页数： | 15/94页 |
| 文件大小： | 1014K |
| 代理商： | BX80526F733256E |
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22
Datasheet
Pentium III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
2.7
Processor System Bus Unused Pins
All RESERVED pins must remain unconnected unless specifically noted. Connection of these pins
to VCCCORE,VREF,VSS,VTT, or to any other signal (including each other) can result in component
malfunction or incompatibility with future processors. See Section 5.4 for a pin listing of the
processor and the location of each RESERVED pin.
PICCLK must be driven with a valid clock input and the PICD[1:0] signals must be pulled-up to
VCCCMOS even when the APIC will not be used. A separate pull-up resistor must be provided for
each PICD signal.
For reliable operation, always connect unused inputs or bidirectional signals to their deasserted
signal level. The pull-up or pull-down resistor values are system dependent and should be chosen
such that the logic high (VIH) and logic low (VIL) requirements are met. See Table 10 and Table 11
for DC specifications of non-AGTL+/AGTL signals.
Unused AGTL+ (or AGTL) inputs must be properly terminated to VTT on PGA370 socket
motherboards which support the Celeron and the Pentium III processors. For designs that intend to
only support the Pentium III processor, unused AGTL+ inputs will be terminated by the processor’s
on-die termination resistors and thus do not need to be terminated on the motherboard. However,
RESET# must always be terminated on the motherboard as the Pentium III processor for the
PGA370 socket does not provide on-die termination of this input.
For unused CMOS inputs, active low signals should be connected through a pull-up resistor to
VCCCMOS and meet VIH requirements. Unused active high CMOS inputs should be connected
through a pull-down resistor to ground (VSS) and meet VIL requirements. Unused CMOS outputs
can be left unconnected. A resistor must be used when tying bidirectional signals to power or
ground. When tying any signal to power or ground, a resistor will also allow for system testability.
2.8
Processor System Bus Signal Groups
To simplify the following discussion, the processor system bus signals have been combined into
groups by buffer type. All P6 family processor system bus outputs are open drain and require a
high-level source provided termination resistors. However, the Pentium III processor for the
PGA370 socket includes on-die termination. Motherboard designs that also support Celeron
processors in the PPGA package will need to provide AGTL+ termination on the system
motherboard as well. Platform designs that support dual processor configurations will need
to provide AGTL+ termination, via a termination package, in any socket not populated with
a processor. Please refer to the Pentium III Processor Specification Update for a complete
listing of the processors that support the AGTL and AGTL+ specifications. Note that AGTL
platforms do not support the Celeron processor in the PPGA package.
Both AGTL+ and AGTL input signals have differential input buffers which use VREF as a reference
signal. AGTL+ output signals require termination to 1.5 V while AGTL output signals require
termination to 1.25 V. In this document, the term “AGTL+ Input” refers to the AGTL+ input group
as well as the AGTL+ I/O group when receiving. Similarly, “AGTL+ Output” refers to the AGTL+
output group as well as the AGTL+ I/O group when driving.
The PWRGOOD, BCLK, and PICCLK inputs can each be driven from ground to 2.5 V. Other
CMOS inputs (A20M#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PREQ#, SMI, SLP#, and
STPCLK#) are only 1.5 V tolerant and must be pulled up to VCCCMOS.The CMOS,APIC, and
TAP outputs are open drain and must be pulled high to VCCCMOS. This ensures correct operation
for current Pentium III and Celeron processors.
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