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参数资料
| 型号： | BX80526F733256E |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 733 MHz, MICROPROCESSOR, PPGA370 |
| 封装： | FCPGA2-370 |
| 文件页数： | 7/94页 |
| 文件大小： | 1014K |
| 代理商： | BX80526F733256E |
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Datasheet
15
Pentium III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
For the processor to fully realize the low current consumption of the Stop-Grant, Sleep and Deep
Sleep states, a Model Specific Register (MSR) bit must be set. For the MSR at 02AH (Hex), bit 26
must be set to a ‘1’ (this is the power on default setting) for the processor to stop all internal clocks
during these modes. For more information, see the Intel Architecture Software Developer’s
Manual, Volume 3: System Programming Guide located on the developer.intel.com website.
2.2.1
Normal State—State 1
This is the normal operating state for the processor.
2.2.2
AutoHALT Powerdown State—State 2
AutoHALT is a low power state entered when the processor executes the HALT instruction. The
processor transitions to the Normal state upon the occurrence of SMI#, INIT#, or LINT[1:0] (NMI,
INTR). RESET# causes the processor to immediately initialize itself.
The return from a System Management Interrupt (SMI) handler can be to either Normal Mode or
the AutoHALT Power Down state. See the Intel Architecture Software Developer's Manual,
Volume III: System Programmer's Guide for more information.
FLUSH# is serviced during the AutoHALT state, and the processor will return to the AutoHALT
state.
Figure 4. Stop Clock State Machine
P C B 757a
2. A u to H A L T P o w er D ow n S tate
B C LK running.
S noops and interrupts allow ed.
H A LT Instruction and
H A LT B us C ycle G enerated
IN IT#, BINIT#, INTR,
SM I#, R ESE T#
1. N o rm al S tate
N orm al execution.
STP C LK #
A sserted
STP C LK #
D e-asserted
3. S top G ran t S tate
BC LK running.
S noops and interrupts allow ed.
SLP #
A sserted
SLP #
D e-asserted
5. S leep S tate
BC LK running.
N o snoops or interrupts allow ed.
BC LK
Input
S topped
BC LK
Input
Restarted
6. D eep S leep S tate
B C LK stopped.
N o snoops or interrupts allow ed.
4. H A L T/G rant S no op S tate
B C LK running.
S ervice snoops to caches.
S noop E vent O ccurs
Snoop E vent Serviced
S noop
E vent
O ccurs
S noop
E vent
Serviced
S T P C LK # A sserted
STPC LK # D e-asserted
and Stop-Grant State
entered from
AutoHALT
, NMI
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