参数资料
型号: BX80526F750256E
厂商: INTEL CORP
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 750 MHz, MICROPROCESSOR, PPGA370
封装: FCPGA2-370
文件页数: 10/94页
文件大小: 1014K
代理商: BX80526F750256E
18
Datasheet
Pentium III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
(1.5 V/1.25 V) are used to provide an AGTL+/AGTL termination voltage to the processor, and the
VREF inputs are used as the AGTL+/AGTL reference voltage for the processor. Note that not all
VTT inputs must be connected to the VTT supply. Refer to Section 5.4 for more details.
On the motherboard, all VCCCORE pins must be connected to a voltage island (an island is a portion
of a power plane that has been divided, or an entire plane). In addition, the motherboard must
implement the VTT pins as a voltage island or large trace. Similarly, all GND pins must be
connected to a system ground plane.
Three additional power related pins exist on a processors utilizing the PGA370 socket. They are
VCC1.5,VCC2.5 and VCCCMOS.
The VCCCMOS pin provides the CMOS voltage for the pull-up resistors required on the system
platform. A 2.5 V source must be provided to the VCC2.5 pin and a 1.5 V source must be provided
to the VCC1.5 pin. The source for VCC1.5 must be the same as the one supplying VTT. The processor
routes the compatible CMOS voltage source (1.5 V or 2.5 V) through the package and out to the
VCCCMOS output pin. Processors based on 0.25 micron technology (e.g., the Celeron processor)
utilize 2.5 V CMOS buffers. Processors based on 0.18 micron technology (e.g., the Pentium III
processor for the PGA370 socket) utilize 1.5 V CMOS buffers. The signal VCOREDET can be used
by hardware on the motherboard to detect which CMOS voltage the processor requires. A
VCOREDET connected to VSS within the processor indicates a 1.5 V requirement on VCCCMOS.
Refer to Figure 5.
Each power signal must meet the specifications stated in Table 7 on page 28.
2.3.1
Phase Lock Loop (PLL) Power
It is highly critical that phase lock loop power delivery to the processor meets Intel’s requirements.
A low pass filter is required for power delivery to pins PLL1 and PLL2. This serves as an isolated,
decoupled power source for the internal PLL. Please refer to the Phase Lock Loop Power section in
the appropriate platform design guide for the recommended filter specifications.
Figure 5. Processor VCCCMOS Package Routing
Intel
Pentium III
Processor
0.1 uF
2.5V Supply
2.5V
1.5V Supply
1.5V
VCC
CMOS
*ICH or
Other Logic
CMOS
Pullups
CMOS Signals
Note: *Ensure this logic is compatible
with 1.5V signal levels of the
Intel Pentium III processor
for the PGA370 socket.
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