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参数资料
| 型号： | BX80526F750256E |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 750 MHz, MICROPROCESSOR, PPGA370 |
| 封装： | FCPGA2-370 |
| 文件页数： | 11/94页 |
| 文件大小： | 1014K |
| 代理商： | BX80526F750256E |
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Datasheet
19
Pentium III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
2.4
Decoupling Guidelines
Due to the large number of transistors and high internal clock speeds, the processor is capable of
generating large average current swings between low and full power states. The fluctuations can
cause voltages on power planes to sag below their nominal values if bulk decoupling is not
adequate. Care must be taken in the board design to ensure that the voltage provided to the
processor remains within the specifications listed in Table 7. Failure to do so can result in timing
violations (in the event of a voltage sag) or a reduced lifetime of the component (in the event of a
voltage overshoot). Unlike SC242 based designs, motherboards utilizing the PGA370 socket
must provide high frequency decoupling capacitors on all power planes for the processor.
2.4.1
Processor VCC
CORE and AGTL+ (AGTL) Decoupling
The regulator for the VCCCORE input must be capable of delivering the dICCCORE/dt (defined in
Table 7) while maintaining the required tolerances (also defined in Table 7). Failure to meet these
specifications can result in timing violations (during VCCCORE sag) or a reduced lifetime of the
component (during VCCCORE overshoot).
The processor requires both high frequency and bulk decoupling on the system motherboard for
proper AGTL+ (AGTL) bus operation. See the AGTL+ buffer specification in the
Intel
Pentium II Processor Developer's Manual for more information. Also, refer to the
appropriate platform design guide for recommended capacitor component placement. The
minimum recommendation for the processor decoupling is listed below. All capacitors should be
placed within the PGA370 socket cavity and mounted on the primary side of the motherboard. The
capacitors are arranged to minimize the overall inductance between the VCCCORE and Vss power
pins.
1. VCCCORE decoupling - 4.7 F capacitors in a 1206 package.
2. VTT decoupling - 0.1 F capacitors in 0603 package.
3. VREF decoupling - 0.1 F and 0.001 F capacitors in 0603 package placed near the VREF pins.
For additional decoupling requirements, please refer to the appropriate platform design guide for
recommended capacitor component value, quantity and placement.
2.5
Processor System Bus Clock and Processor Clocking
The BCLK input directly controls the operating speed of the system bus interface. All AGTL+/
AGTL system bus timing parameters are specified with respect to the rising edge of the BCLK
input.
The Coppermine-T processor will implement an auto-detect mechanism that will let the processor
use either single-ended or differential signaling for the system bus and processor clocking. The
processor checks to see if the signal on pin Y33 is toggling. If this signal is toggling then the
processor operates in differential mode. Refer to Figure 6 for a differential clocking example.
Resistor values and clock topology are listed in the appropriate platform design guide for a
differential implementation.
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