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| 型号： | BXM80526B700128 |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 64-BIT, 700 MHz, MICROPROCESSOR, CPGA495 |
| 封装： | MICRO, PGA2-495 |
| 文件页数： | 14/74页 |
| 文件大小： | 870K |
| 代理商： | BXM80526B700128 |
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Mobile Intel Celeron Processor (0.18) in BGA2 and Micro-PGA2 Packages
at 700MHz, 650 MHz, 600 MHz, 550 MHz, 500 MHz, 450 MHz,
Low-voltage 500 MHz, and Low-voltage 400A MHz
Datasheet
Order#-XXX
14
3.3
System Bus Clock and Processor Clocking
The 2.5-V BCLK clock input directly controls the operating speed of the system bus interface. All
system bus timing parameters are specified with respect to the rising edge of the BCLK input. The
mobile Celeron processor core frequency is a multiple of the BCLK frequency. The processor core
frequency is configured during manufacturing. The configured bus ratio is visible to software in
the Power-on configuration register, see Section 7.2 for details.
Multiplying the bus clock frequency is necessary to increase performance while allowing for
easier distribution of signals within the system. Clock multiplication within the processor is
provided by the internal Phase Lock Loop (PLL), which requires a constant frequency BCLK
input. During Reset or on exit from the Deep Sleep state, the PLL requires some amount of time to
acquire the phase of BCLK. This time is called the PLL lock latency, which is specified in
Section 3.6, AC timing parameters T18 and T47.
3.4
Maximum Ratings
Table 8 contains the mobile Celeron processor stress ratings. Functional operation at the absolute
maximum and minimum is neither implied nor guaranteed. The processor should not receive a
clock while subjected to these conditions. Functional operating conditions are provided in the AC
and DC tables. Extended exposure to the maximum ratings may affect device reliability.
Furthermore, although the processor contains protective circuitry to resist damage from static
electric discharge, one should always take precautions to avoid high static voltages or electric
fields.
Table 8. Mobile Celeron Processor Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Unit
Notes
TStorage
Storage Temperature
–40
85
°C
Note 1
VCC(Abs)
Supply Voltage with respect to VSS
–0.5
2.1
V
VCCT
System Bus Buffer Voltage with respect to VSS
–0.3
2.1
V
VIN GTL
System Bus Buffer DC Input Voltage with respect to VSS –0.3
2.1
V
Notes 2, 3
VIN GTL
System Bus Buffer DC Input Voltage with respect to VCCT —VCCT + 0.7V V
Notes 2, 4
VIN15
1.5V Buffer DC Input Voltage with respect to VSS
–0.3
2.1
V
Note 5
VIN25
2.5V Buffer DC Input Voltage with respect to VSS
–0.3
3.3
V
Note 6
VIN33
3.3V Buffer DC Input Voltage with respect to VSS
–0.3
3.5
V
Note 7
VINVID
VID ball/pin DC Input Voltage with respect to VSS
—5.5
V
IVID
VID Current
5
mA
Note 8
NOTES:
1.
The shipping container is only rated for 65°C.
2.
Parameter applies to the GTL+ signal groups only. Compliance with both VIN GTL specifications is required.
3.
The voltage on the GTL+ signals must never be below –0.3 or above 2.1V with respect to ground.
4.
The voltage on the GTL+ signals must never be above VCCT + 0.7V even if it is less than VSS + 2.1V, or a short to ground
may occur.
5.
Parameter applies to CMOS, Open-drain, APIC, and TAP bus signal groups only.
6.
Parameter applies to BCLK, CLKREF, PICCLK and PWRGOOD signals.
7.
Parameter applies to BSEL[1:0] signals.
8.
Parameter applies to each VID pin/ball individually.
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