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| 型号： | BXM80536GC1800F |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 1800 MHz, MICROPROCESSOR, CPGA478 |
| 封装： | FLIP CHIP, PGA-478 |
| 文件页数： | 11/84页 |
| 文件大小： | 1488K |
| 代理商： | BXM80536GC1800F |
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Datasheet
19
Electrical Specifications
3.4
Signal Terminations and Unused Pins
All RSVD (RESERVED) pins must remain unconnected. Connection of these pins to VCC, VSS, or
to any other signal (including each other) can result in component malfunction or incompatibility
with future Pentium M processors. See Section 4.2 for a pin listing of the processor and the
location of all RSVD pins.
For reliable operation, always connect unused inputs or bidirectional signals to an appropriate
signal level. Unused active low AGTL+ inputs may be left as no connects if AGTL+ termination is
provided on the processor silicon. Unused active high inputs should be connected through a resistor
to ground (VSS). Unused outputs can be left unconnected.
For details on signal terminations, please refer to the platform design guides.
The TEST1 and TEST2 pins must have a stuffing option connection to VSS separately via 1-kΩ,
pull-down resistors.
3.5
FSB Frequency Select Signals (BSEL[1:0])
These signals are used to select the FSB clock frequency. They should be connected between the
processor and the chipset MCH and clock generator on Intel 915 Express chipset family based
platforms. These signals must be left unconnected on platforms designed with the Intel 855 chipset
family. On these platforms, FSB clock frequency should be configured on the motherboard.
3.6
FSB Signal Groups
In order to simplify the following discussion, the FSB signals have been combined into groups by
buffer type. AGTL+ input signals have differential input buffers, which use GTLREF as a reference
level. In this document, the term "AGTL+ Input" refers to the AGTL+ input group as well as the
AGTL+ I/O group when receiving. Similarly, "AGTL+ Output" refers to the AGTL+ output group
as well as the AGTL+ I/O group when driving.
With the implementation of a source synchronous data bus comes the need to specify two sets of
timing parameters. One set is for common clock signals which are dependant upon the rising edge
of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second set is for the source synchronous signals
which are relative to their respective strobe lines (data and address) as well as the rising edge of
BCLK0. Asychronous signals are still present (A20M#, IGNNE#, etc.) and can become active at
any time during the clock cycle. Table 3-2 identifies which signals are common clock, source
synchronous, and asynchronous.
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相关代理商/技术参数 |
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| BXM80536NC1400ES L7LS | 制造商:Intel 功能描述:CELERON M,360,1.40GHZ,1M CACHE, 400MHZ FSB,1.26V,UFCPGA - Boxed Product (Development Kits) |
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| BXMP1001 | 制造商:SPECTRUM 制造商全称:Spectrum Microwave, Inc. 功能描述:RF AMPLIFIER |
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