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参数资料
| 型号： | BXM80536GC2100F |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 2100 MHz, MICROPROCESSOR, CPGA478 |
| 封装： | FLIP CHIP, PGA-478 |
| 文件页数： | 6/84页 |
| 文件大小： | 1488K |
| 代理商： | BXM80536GC2100F |
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14
Datasheet
Low Power Features
2.1.7
Deeper Sleep State
The Deeper Sleep state is the lowest power state the processor can enter. This state is functionally
identical to the Deep Sleep state but at a lower core voltage. The control signals to the voltage
regulator to initiate a transition to the Deeper Sleep state are provided on the platform. Please refer
to the platform design guides listed in Table 1-1.
2.2
Enhanced Intel SpeedStep Technology
The Pentium M processor features Enhanced Intel SpeedStep technology. Unlike previous
implementations of Intel SpeedStep technology, this technology enables the processor to switch
between multiple frequency and voltage points instead of two. This will enable superior
performance with optimal power savings. Switching between states is software controlled unlike
previous implementations where the GHI# pin is used to toggle between two states. Following are
the key features of Enhanced Intel SpeedStep technology:
Multiple voltage/frequency operating points provide optimal performance at the lowest power.
Voltage/Frequency selection is software controlled by writing to processor MSR’s (Model
Specific Registers) thus eliminating chipset dependency.
— If the target frequency is higher than the current frequency, Vcc is ramped up by placing a
new value on the VID pins and the PLL then locks to the new frequency.
— If the target frequency is lower than the current frequency, the PLL locks to the new
frequency and the Vcc is changed through the VID pin mechanism.
— Software transitions are accepted at any time. If a previous transition is in progress, the
new transition is deferred until its completion.
The processor controls voltage ramp rates internally to ensure glitch free transitions.
Low transition latency and large number of transitions possible per second.
— Processor core (including L2 cache) is unavailable for up to 10
μs during the frequency
transition
— The bus protocol (BNR# mechanism) is used to block snooping
No bus master arbiter disable required prior to transition and no processor cache flush
necessary.
Improved Intel Thermal Monitor mode.
— When the on-die thermal sensor indicates that the die temperature is too high, the
processor can automatically perform a transition to a lower frequency/voltage specified in
a software programmable MSR.
— The processor waits for a fixed time period. If the die temperature is down to acceptable
levels, an up transition to the previous frequency/voltage point occurs.
— An interrupt is generated for the up and down Intel Thermal Monitor transitions enabling
better system level thermal management.
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