参数资料
型号: C167CS-L16M3V
厂商: INFINEON TECHNOLOGIES AG
英文描述: 16-Bi t Single-Chip Microcontroller
中文描述: 16碧吨单片机
文件页数: 18/81页
文件大小: 1198K
代理商: C167CS-L16M3V
C167CS-L16M3V
Low Power
Data Sheet
14
V1.0, 2001-10
Functional Description
The architecture of the C167CS-3V combines advantages of both RISC and CISC
processors and of advanced peripheral subsystems in a very well-balanced way. In
addition the on-chip memory blocks allow the design of compact systems with maximum
performance.
The following block diagram gives an overview of the different on-chip components and
of the advanced, high bandwidth internal bus structure of the C167CS-3V.
Note:
All time specifications refer to a CPU clock of 16 MHz
(see definition in the AC Characteristics section).
Figure 3
Block Diagram
The program memory, the internal RAM (IRAM) and the set of generic peripherals are
connected to the CPU via separate buses. A fourth bus, the XBUS, connects external
resources as well as additional on-chip resoures, the X-Peripherals (see
Figure 3
).
The XBUS resources (XRAM, CAN) of the C167CS-3V can be individually enabled or
disabled during initialization. Register XPERCON selects the required modules which
are then enabled by setting the general X-Peripheral enable bit XPEN (SYSCON.2).
Modules that are disabled consume neither address space nor port pins.
Note: The default value of register XPERCON after reset selects 2 KByte XRAM and
module CAN1, so the default XBUS resources are compatible with the C167CR.
C166-Core
CPU
P
Interrupt Bus
XTAL
Osc / PLL
RTC
WDT
32
16
Interrupt Controller
16-Level
Priority
PEC
External Instr. / Data
GPT
T2
T3
T4
T5
T6
SSC
(SPI)
BRGen
ASC0
(USART)
BRGen
ADC
10-Bit
16+8
Channels
PWM
CCOM1
T0
T1
CCOM2
T7
T8
EBC
XBUS Control
External Bus
Control
IRAM
Internal
RAM
3 KByte
D
ProgMem
ROM
32 KByte
Data
Data
16
16
16
CAN1
Rev 2.0B active
Instr. / Data
Port 0
XRAM
6+2 KByte
P
8
8
Port 1
16
16
16
Port 5
Port 3
15
Port 7
8
Port 8
8
P
16
Peripheral Data Bus
16
CAN2
Rev 2.0B active
O
MCB04323_7CS
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