参数资料
型号: C167CS-L16M3V
厂商: INFINEON TECHNOLOGIES AG
英文描述: 16-Bi t Single-Chip Microcontroller
中文描述: 16碧吨单片机
文件页数: 5/81页
文件大小: 1198K
代理商: C167CS-L16M3V
Data Sheet
1
V1.0, 2001-10
C167CS-3V
16-Bit Single-Chip Microcontroller
C166 Family
C167CS-3V
High Performance 16-bit CPU with 4-Stage Pipeline
– 125 ns Instruction Cycle Time at 16 MHz CPU Clock
– 625 ns Multiplication (16
×
16 bit), 1250 ns Division (32/16 bit)
– Enhanced Boolean Bit Manipulation Facilities
– Additional Instructions to Support HLL and Operating Systems
– Register-Based Design with Multiple Variable Register Banks
– Single-Cycle Context Switching Support
– 16 MBytes Total Linear Address Space for Code and Data
– 1024 Bytes On-Chip Special Function Register Area
16-Priority-Level Interrupt System with 56 Sources, Sample-Rate down to 62 ns
8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via
Peripheral Event Controller (PEC)
Clock Generation via on-chip PLL (factors 1:1.5/2/2.5/3/4/5),
via prescaler or via direct clock input
On-Chip Memory Modules
– 3 KBytes On-Chip Internal RAM (IRAM)
– 8 KBytes On-Chip Extension RAM (XRAM)
On-Chip Peripheral Modules
– 24-Channel 10-bit A/D Converter with Programmable Conversion Time
down to 7.8
μ
s
– Two 16-Channel Capture/Compare Units
– 4-Channel PWM Unit
– Two Multi-Functional General Purpose Timer Units with 5 Timers
– Two Serial Channels (Synchronous/Asynchronous and High-Speed-Synchronous)
– Two On-Chip CAN Interfaces (Rev. 2.0B active) with 2
×
15 Message Objects
(Full CAN/Basic CAN), can work on one bus with 30 objects
– On-Chip Real Time Clock
Up to 16 MBytes External Address Space for Code and Data
– Programmable External Bus Characteristics for Different Address Ranges
– Multiplexed or Demultiplexed External Address/Data Buses with 8-Bit or 16-Bit
Data Bus Width
– Five Programmable Chip-Select Signals
– Hold- and Hold-Acknowledge Bus Arbitration Support
Idle, Sleep, and Power Down Modes with Flexible Power Management
Programmable Watchdog Timer and Oscillator Watchdog
Up to 111 General Purpose I/O Lines,
partly with Selectable Input Thresholds and Hysteresis
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