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参数资料
| 型号： | C1851BCU |
| 厂商： | NEC Corp. |
| 英文描述： | I2C BUS-COMPATIBLE US MTS PROCESSING LSI |
| 中文描述： | I2C总线兼容美国的多边贸易体制处理LSI |
| 文件页数： | 10/60页 |
| 文件大小： | 447K |
| 代理商： | C1851BCU |
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18
PC1851B
Data Sheet S13417EJ2V0DS00
2. BLOCK FUNCTIONS
2.1 Stereo Demodulation Block
(1) Stereo LPF
This filter eliminates signals in the vicinity of 5 fH to 6 fH, such as SAP (Sub Audio Program) (5 fH) and telemetry
signals (6.5 fH) . The
PC1851B’s internal L–R demodulator, which uses a double-balanced circuit, demodulates
L–R signals by multiplication of the L–R signal with the signal at the L–R carrier frequency (2 fH). The L–R signal
tends to receive interference from the 6 fH signal because a square waveform is used as the switching carrier in this
method. To eliminate this interference, the
PC1851B incorporates traps at 5 fH and 6 fH. The filter response is
adjusted by setting the FILTER SETTING bits (Write register, subaddress 02H, bits D0 to D5).
(2) Stereo Phase Comparator
The 8 fH signal generated at the Stereo VCO is divided by 8 (4
× 2) and then multiplied by the pilot signal passed
through the stereo LPF. The two signals differ from each other by 90 degrees in terms of phase.
The resistor and capacitor connected to the
φD1 and φD2 pins form a filter that smoothes the phase error signal
output from the Stereo Phase Comparator, converting the error signal to the DC voltage. When the voltage difference
between
φD1 and φD2 pins becomes 0 V (strictly speaking, not 0 V by the internal offset voltage), the VCO runs at
8 fH.
The lag/lead filter externally connected to the pins
φD1 and φD2 determines the capture range.
(3) Stereo VCO
The Stereo VCO runs at 8 fH with the internal capacitor. The frequency is adjusted by setting the STEREO VCO
SETTING bits (Write register, subaddress 01H, bits D0 to D5).
(4) Divider (Flip-flop)
Produces two separate fH signals: the inphase fH signal, and the fH signal differing by 90 degrees from the input
pilot signal by dividing the 8 fH frequency from the Stereo VCO by 8 (4
× 2).
(5) Pilot Discrimination Phase Comparator (Level detector)
Multiplies the pilot signal from the COM pin with the inphase fH signal from the divider. The resulting signal is
smoothed by passing it through the external filter connected to the PD1 and PD2 pins and converted into DC
voltage that is used to determine whether or not a stereo pilot is present (Read register, bit D6).
(6) Pilot Canceler
The fH signal from the divider is added to the stereo signal matrix depending on the level of the input pilot signal
to cancel the pilot signal.
(7) L+R LPF
This LPF which has traps at fH and 24 kHz, allows only the monaural signal to pass through. The filter response
is adjusted by setting the FILTER SETTING bit (Write register, subaddress 02H, bits D0 to D5).
(8) De-emphasis
The 75-
s de-emphasis filter is for the monaural signal. The response is adjusted by setting the FILTER SETTING
bit (Write register, subaddress 02H, bits D0 to D5).
(9) L–R AM Demodulator
Demodulates the L–R AM-DSB modulated signal by multiplying with the 2-fH signal which is synchronized to the
pilot signal. The 2-fH square wave is used as the switching carrier.
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