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参数资料
| 型号： | C1851BCU |
| 厂商： | NEC Corp. |
| 英文描述： | I2C BUS-COMPATIBLE US MTS PROCESSING LSI |
| 中文描述： | I2C总线兼容美国的多边贸易体制处理LSI |
| 文件页数： | 18/60页 |
| 文件大小： | 447K |
| 代理商： | C1851BCU |
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25
PC1851B
Data Sheet S13417EJ2V0DS00
(1) 1-byte data transfer
The format for 1-byte data transfer is the following:
(2) Continuous data transfer
The format when transferring multiple (7) bytes of data at one time by using the automatic increment function is
the following:
The master CPU transfers “00H” as subaddress SA0 following the start condition and slave address. After the
subaddress SA0, the master CPU transfers the SA0 data, and continues with SA1, SA2,..., SAA data without transferring
stop conditions in between. Finally, the stop condition is transferred and the transfer is completed.
(3) Data read
The
PC1851B has one read register. The contents of this register can be read by the master CPU.
The format when data is read is the following:
(4) Acknowledge
In the case of the I2C bus, an acknowledge bit is added to the data as the 9th bit to determine whether data
transfer was successful. The master CPU determines the success or failure of data transfer based on whether this
acknowledge bit is a logical low or high.
If the acknowledge interval is a logical low, this indicates that data transfer was successful. If it is a logical high,
this indicates that data transfer was unsuccessful or that the slave side forcibly released the bus.
Start
Slave
address
Write
mode
Acknow
-ledge
Subaddress
Acknow
-ledge
Data
Acknow
-ledge
Stop
Start
Slave
address
Write
mode
Acknow
-ledge
Subaddress
Acknow
-ledge
Data1
Acknow
-ledge
Data2
Acknow
-ledge
Acknow
-ledge
Stop
Data7
Start
Slave
address
Acknow
-ledge
Data
Non-
acknow
-ledge
Stop
Read
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