参数资料
型号: C8051F016
厂商: Silicon Laboratories Inc
文件页数: 12/171页
文件大小: 0K
描述: IC 8051 MCU 32K FLASH 48TQFP
标准包装: 250
系列: C8051F01x
核心处理器: 8051
芯体尺寸: 8-位
速度: 25MHz
连通性: SMBus(2 线/I²C),SPI,UART/USART
外围设备: 欠压检测/复位,POR,PWM,温度传感器,WDT
输入/输出数: 16
程序存储器容量: 32KB(32K x 8)
程序存储器类型: 闪存
RAM 容量: 2.25K x 8
电压 - 电源 (Vcc/Vdd): 2.7 V ~ 3.6 V
数据转换器: A/D 8x10b; D/A 2x12b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 48-TQFP
包装: 托盘
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
15.3.
General Purpose Port I/O
Each MCU has four byte-wide, bi-directional parallel ports that can be used general purpose I/O. Each port is
accessed through a corresponding special function register (SFR) that is both byte addressable and bit addressable.
When writing to a port, the value written to the SFR is latched to maintain the output data value at each pin. When
reading, the logic levels of the port’s input pins are returned regardless of the XBRn settings (i.e. even when the pin
is assigned to another signal by the Crossbar, the Port Register can always still read its corresponding Port I/O pin).
The exception to this is the execution of the read-modify-write instructions. The read-modify-write instructions
when operating on a port SFR are the following: ANL, ORL, XRL, JBC, CPL, INC, DEC, DJNZ and MOV, CLR
or SET, when the destination is an individual bit in a port SFR. For these instructions, the value of the port register
(not the pin) is read, modified, and written back to the SFR.
15.4.
Configuring Ports Which are not Pinned Out
P2 and P3 are not pinned out on the F001/06/11/16. P1, P2, and P3 are not pinned out on the F002/07/12/17. These
port registers (and corresponding interrupts, where applicable) are still available for software use in these reduced
pin count MCUs. Whether used or not in software, it is recommended not to let these port drivers go to high
impedance state. This is prevented after reset by having the weak pull-ups enabled as described in the XBR2
register. It is recommended that each output driver for ports not pinned out should be configured as push-pull using
the corresponding PRTnCF register. This will inhibit a high impedance state even if the weak pull-up is disabled.
Figure 15.6. P0: Port0 Register
R/W
Reset Value
P0.7
P0.6
P0.5
P0.4
P0.3
P0.2
P0.1
P0.0
11111111
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
(bit addressable)
0x80
Bits7-0: P0.[7:0]
(Write – Output appears on I/O pins per XBR0, XBR1, and XBR2 Registers)
0: Logic Low Output.
1: Logic High Output (high-impedance if corresponding PRT0CF.n bit = 0)
(Read – Regardless of XBR0, XBR1, and XBR2 Register settings).
0: P0.n pin is logic low.
1: P0.n pin is logic high.
Figure 15.7. PRT0CF: Port0 Configuration Register
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0xA4
Bits7-0: PRT0CF.[7:0]: Output Configuration Bits for P0.7-P0.0 (respectively)
0: Corresponding P0.n Output mode is Open-Drain.
1: Corresponding P0.n Output mode is Push-Pull.
(Note:
When SDA, SCL, and RX appear on any of the P0 I/O, each are open-drain
regardless of the value of PRT0CF).
109
Rev. 1.7
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